The VS pin is used to sense the positive voltage level of the auxiliary winding voltage (V_AUX) to detect an over-voltage condition of V_O. When an OVP event is triggered, the auto-recovery version of OVP stops switching and there is a 1.5-s fault recovery time (t_FDR) before any V_O restart attempt is made. As Q_L turns off, the settled V_AUX is equal to (V_O+V_F) x N_AS, where N_AS is the auxiliary-to-secondary turns ratio of the transformer, N_A / N_S, and V_F is the forward voltage drop of the secondary-side rectifier. The VS pin senses V_AUX through a voltage divider formed by R_VS1 and R_VS2. The pin voltage (V_VS) is compared with an internal OVP threshold (V_OVP). If V_VS ≥ V_OVP condition is qualified for three consecutive PWML pulses, the controller stops switching, brings RUN pin low, and initiates the 1.5-s time delay. During this long delay time, only the UVLO-cycle of V_VDD is active, and there are no test pulses of PWML. After the 1.5-s timeout is completed and V_VDD reaches the next V_VDD(OFF), a normal start sequence begins. The calculation of R_VS2 is

Equation 18.

The long t_FDR timer (1.5 s) helps to protect the power stage components from the large current stress during every restart and allows some time for V_O to discharge in the case of light-load or no-load, before attempting restart.