ZHCSLD2E may   2020  – july 2023 UCC28782

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 描述
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Detailed Pin Description
      1. 8.3.1  BUR Pin (Programmable Burst Mode)
      2. 8.3.2  FB Pin (Feedback Pin)
      3. 8.3.3  REF Pin (Internal 5-V Bias)
      4. 8.3.4  VDD Pin (Device Bias Supply)
      5. 8.3.5  P13 and SWS Pins
      6. 8.3.6  S13 Pin
      7. 8.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 8.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 8.3.9  PWMH and AGND Pins
      10. 8.3.10 PWML and PGND Pins
      11. 8.3.11 SET Pin
      12. 8.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 8.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 8.3.14 BIN, BSW, and BGND Pins
      15. 8.3.15 XCD Pin
      16. 8.3.16 CS, VS, and FLT Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 8.4.2  Dead-Time Optimization
      3. 8.4.3  EMI Dither and Dither Fading Function
      4. 8.4.4  Control Law across Entire Load Range
      5. 8.4.5  Adaptive Amplitude Modulation (AAM)
      6. 8.4.6  Adaptive Burst Mode (ABM)
      7. 8.4.7  Low Power Mode (LPM)
      8. 8.4.8  First Standby Power Mode (SBP1)
      9. 8.4.9  Second Standby Power Mode (SBP2)
      10. 8.4.10 Startup Sequence
      11. 8.4.11 Survival Mode of VDD (INT_STOP)
      12. 8.4.12 Capacitor Voltage Balancing Function
      13. 8.4.13 Device Functional Modes for Bias Regulator Control
        1. 8.4.13.1 Mitigation of Switching Interaction with ACF Converter
        2. 8.4.13.2 Protection Functions for the Bias Regulator
        3. 8.4.13.3 BIN-Pin Related Protections
        4. 8.4.13.4 BSW-Pin Related Protections
      14. 8.4.14 System Fault Protections
        1. 8.4.14.1  Brown-In and Brown-Out
        2. 8.4.14.2  Output Over-Voltage Protection (OVP)
        3. 8.4.14.3  Input Over Voltage Protection (IOVP)
        4. 8.4.14.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 8.4.14.5  Over-Temperature Protection (OTP) on CS Pin
        6. 8.4.14.6  Programmable Over-Power Protection (OPP)
        7. 8.4.14.7  Peak Power Limit (PPL)
        8. 8.4.14.8  Output Short-Circuit Protection (SCP)
        9. 8.4.14.9  Over-Current Protection (OCP)
        10. 8.4.14.10 External Shutdown
        11. 8.4.14.11 Internal Thermal Shutdown
      15. 8.4.15 Pin Open/Short Protections
        1. 8.4.15.1 Protections on CS pin Fault
        2. 8.4.15.2 Protections on P13 pin Fault
        3. 8.4.15.3 Protections on RDM and RTZ pin Faults
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application Circuit
      1. 9.2.1 Design Requirements for a 65-W USB-PD Adapter Application
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 9.2.2.2 Transformer Calculations
          1. 9.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 9.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 9.2.2.2.3 Primary Winding Turns (NP)
          4. 9.2.2.2.4 Secondary Winding Turns (NS)
          5. 9.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 9.2.2.2.6 Winding and Magnetic Core Materials
        3. 9.2.2.3 Clamp Capacitor Calculation
          1. 9.2.2.3.1 Primary-Resonance ACF
          2. 9.2.2.3.2 Secondary-Resonance ACF
        4. 9.2.2.4 Bleed-Resistor Calculation
        5. 9.2.2.5 Output Filter Calculation
        6. 9.2.2.6 Calculation of ZVS Sensing Network
        7. 9.2.2.7 Calculation of BUR Pin Resistances
        8. 9.2.2.8 Calculation of Compensation Network
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  General Considerations
      2. 11.1.2  RDM and RTZ Pins
      3. 11.1.3  SWS Pin
      4. 11.1.4  VS Pin
      5. 11.1.5  BUR Pin
      6. 11.1.6  FB Pin
      7. 11.1.7  CS Pin
      8. 11.1.8  BIN Pin
      9. 11.1.9  BSW Pin
      10. 11.1.10 AGND Pin
      11. 11.1.11 BGND Pin
      12. 11.1.12 PGND Pin
      13. 11.1.13 EP Thermal Pad
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

IPC Pin (Intelligent Power Control Pin)

Under certain conditions, the IPC pin provides a 50-µA current from an internal source (IIPC(SBP2)) which is controlled by logic as shown in Figure 8-9. The voltage on the VS pin is sampled during the demagnetization time to obtain an indication of the reflected output voltage (NVO). When the VS-pin voltage is lower than the 2.4-V lower LV mode threshold (VVSLV(LR)), the LOW_NVO logic signal is pulled high, and the current source is enabled during the run state of all normal control modes (SBP1, SBP2, LPM, ABM, and AAM).

When the sampled VS-pin voltage is higher than the 2.5-V upper LV mode threshold (VVSLV(UP)), the LOW_NVO logic signal becomes low. In the LOW_NVO = 0 V case, the 50-µA current source is enabled in the run state of SBP2 mode only.

To minimize stand-by power, the 50-µA source is always disabled during the wait state of any control mode. Additionally, if VVDD falls lower than the 13-V survival-mode threshold, the INT_STOP logic signal is pulled high and the current source is disabled during survival mode operation, irrespective of the VVS level.

GUID-4C31D6EB-42D0-445B-B7E4-086C0C819C81-low.gifFigure 8-9 Control Circuit Diagram to the IPC-Pin Current Source

The multi-function IPC pin can be programmed to obtain one or more of the following benefits:

  1. Reduction of input power for special light-load and stand-by conditions.

  2. Improvement of light-load efficiency at lower output voltages, such as 5 V and 9 V.

  3. Reduction of burst-mode output ripple at lower output voltages.

  4. Reduction of the over-power limit at lower output voltages.

  5. Power management of a PFC controller, together with the S13 pin.

To implement the 1st benefit, a resistor RIPC is connected from IPC pin to AGND pin. The 50-µA current source establishes a voltage (VIPC) across RIPC to program an increase in the CS-pin peak primary current threshold at very light loads. The transfer function between VIPC and the CS threshold (VCST_IPC) in SBP2 mode is illustrated in Figure 8-10.

Proper sizing of RIPC to AGND can further reduce the burst frequency in SBP2 for so-called "tiny-load" power and for stand-by power. An example of a tiny-load input power specification is that the input power must be less than 0.5 W when the output power is 0.25 W at the 20-V output. An example of a stand-by power specification is that the input power must be less than 75 mW at no load at the 5-V output.

When VIPC is less than 0.9 V (or IPC is shorted to AGND), VCST_IPC threshold stays at the minimum level of 0.15 V. When VIPC is set between 0.9 V and 1.8V, VCST_IPC is clamped at 0.27 V. For VIPC between 1.8 V and 3.8 V, there is a linear programmable VCST_IPC range between 0.27 V and 0.4 V. When VIPC is greater than 3.8 V, VCST_IPC remains clamped to 0.4 V. Be aware that high settings of VCST_IPC may, in some cases, introduce higher output ripple in deep light-load condition or provoke audible noise.

GUID-0FE2F127-1169-40B9-80F9-FF0860DBD399-low.gifFigure 8-10 IPC Transfer Function to Program the SBP2 Peak Current Threshold

Since the enable status of the IPC current source contains the very useful output voltage information from the LOW_NVO logic state, the IPC pin can be used to further optimize power stage performance over a wide output voltage range. To gain the 2nd, 3rd, and 4th benefits of the IPC function, RIPC should be connected between the IPC pin and the CS pin, so that the current source can create additional CS-pin offset voltage on ROPP when VVS < 2.4 V. With higher CS offset, the operating range of the VCST signal will be higher than the actual power stage peak current. This forces the controller to operate in AAM mode for a wider actual output load range, and forces the burst-mode threshold down to a lower power level.

For 100-W USB-PD adapters as example, the 20-V output is designed to deliver 100 W full power, but the 5-V output requires only 15 W full power. When the 20-V output enters ABM below 50 W, the majority of the 5-V output load range may operate in burst mode. Figure 8-11 compares the control law difference between the two IPC-pin connections.

When RIPC is connected to AGND, the peak magnetizing current (iM(+)) correlated with the VCST(BUR) setting of the higher power 20-V output is too high for the lower-power 5-V output. With higher energy per cycle at the 5-V output, the AAM mode must transition into ABM mode at a heavier load condition, and the hard switching operating modes such as LPM will cover a wider output load range. Therefore, the 5-V average efficiency is impaired by the hard switching operation, and the output ripple is compromised by the burst mode setting.

When the RIPC is connected to CS, however, the output voltage feedback loop increases the VCST level to overcome the CS offset voltage in AAM, such that the AAM-ABM transition point can be pushed to a lighter output load. Since the output load range covered by the soft switching operating modes (AAM and ABM) is extended with this IPC configuration, the average efficiency at the low-power voltage levels can be improved. Moreover, since the peak current becomes lower in burst mode, the output ripple magnitude is reduced as well.

Figure 8-11 points out the side effect of the IPC-to-CS connection if the RIPC setting is the same. Since 50 µA is enabled in the run state of SBP2, the lower peak magnetizing current of the IPC-to-CS connection makes the SBP2 burst frequency higher and results in weakening the stand-by power improvement. Therefore, a higher RIPC is needed to increase VCST_IPC to compensate the peak current change.

GUID-D702EC4C-43FF-4DD2-851A-254295E2651F-low.gifFigure 8-11 Effect of the CS-pin Offset Voltage from the IPC Pin

For the 5th benefit, the IPC pin can also be used to disable a PFC controller (if used) at all load conditions for 5-V and 9-V outputs to further improve the light-load efficiency of higher power adapters. As shown in Figure 8-7, the diode DIPC in series with RIPC is placed between IPC and CS pins, and VIPC established at IPC is used to drive a small-signal switch QIPC to disable the PFC controller such as UCC28056.

When VIPC is higher than its threshold voltage, QIPC can pull low the COMP pin voltage of a PFC controller, so its switching is disabled. As a consequence, PFC output voltage drops from the typical 400-V regulation level to the peak value of the AC line. This lowers the ACF bulk voltage, which reduces the ZVS energy, which increases ACF power stage efficiency for low voltage outputs. Furthermore, the power loss of the PFC power stage is out of the efficiency equation. One design example for those components are CS13(ACF) = 22 nF, CS13(PFC) = 0.22 µF, CIPC = 10 nF, RIPC = 69.8 kΩ, RIPC2 = 10 MΩ, and RIPC3 = 20 kΩ. Choose QIPC with threshold voltage less than 1.5 V to ensure that VIPC is sufficient to achieve low Rds(on) even at very low burst frequencies.