7.3.1 Start-Up Protection Logic

Before the UCC28950 controller will start up, the following conditions must be met:

• VDD voltage exceeds rising UVLO threshold 7.3-V typical.
• The 5-V reference voltage is available.
• Junction temperature is below the thermal shutdown threshold of 140°C.
• The voltage on the soft-start capacitor is not below 0.55-V typical.

If all those conditions are met, an internal enable signal EN is generated that initiates the soft start process. The duty cycle during the soft start is defined by the voltage at the SS pin, and cannot be lower than the duty cycle set by TMIN, or by cycle-by-cycle current limit circuit depending on load conditions.

7.3.2 Voltage Reference (VREF)

The accurate (±1.5%) 5-V reference voltage regulator with a short circuit protection circuit supplies internal circuitry and provides up to 20-mA external output current. Place a low ESR and ESL, preferably ceramic decoupling capacitor C_REF in 1-µF to 2.2-µF range from this pin to GND as close to the related pins as possible for best performance. The only condition where the reference regulator is shut down internally is during under voltage lockout.

7.3.3 Error Amplifier (EA+, EA–, COMP)

The error amplifier has two uncommitted inputs, EA+ and EA-, with a 3-MHz unity gain bandwidth, which allows flexibility in closing the feedback loop. The EA+ is a non-inverting input, the EA– is an inverting input and the COMP is the output of the error amplifier. The input voltage common mode range, where the parameters of the error amplifier are guaranteed, is from 0.5 V to 3.6 V. The output of the error amplifier is connected internally to the non-inverting input of the PWM comparator. The range of the error amplifier output of 0.25 V to 4.25 V far exceeds the PWM comparator input ramp-signal range, which is from 0.8 V to 2.8 V. The soft-start signal serves as an additional non-inverting input of the error amplifier. The lower of the two non-inverting inputs of the error amplifier is the dominant input and sets the duty cycle where the output signal of the error amplifier is compared with the internal ramp at the inputs of the PWM comparator.

7.3.4 Soft Start and Enable (SS/EN)

The soft-start pin SS/EN is a multi-function pin used for the following operations:

• Closed loop soft start with the gradual duty cycle increase from the minimum set by TMIN up to the steady state duty cycle required by the regulated output voltage.
• Setting hiccup mode conditions during cycle-by-cycle overcurrent limit.
• On/off control for the converter.

During soft start, one of the voltages at the SS/EN or EA+ pins, whichever is lower (SS/EN – 0.55 V) or EA+ voltage (see Block Diagram), sets the reference voltage for a closed feedback loop. Both SS/EN and EA+ signals are non-inverting inputs of the error amplifier with the COMP pin being its output. Thus the soft start always goes under the closed feedback loop and the voltage at COMP pin sets the duty cycle. The duty cycle defined by the COMP pin voltage can not be shorter than TMIN pulse width set by the user. However, if the shortest duty cycle is set by the cycle-by-cycle current limit circuit, then it becomes dominant over the duty cycle defined by the COMP pin voltage or by the TMIN block.

The soft-start duration is defined by an external capacitor C_SS, connected between the SS/EN pin and ground, and the internal charge current that has a typical value of 25 µA. Pulling the soft-start pin externally below 0.55 V shuts down the controller. The release of the soft-start pin enables the controller to start, and if there is no current limit condition, the duty cycle applied to the output inductor gradually increases until it reaches the steady state duty cycle defined by the regulated output voltage of the converter. This happens when the voltage at the SS/EN pin reaches and then exceeds by 0.55 V, the voltage at the EA+ pin. Thus for the given soft-start time T_SS, the C_SS value can be defined by Equation 1 or Equation 2:

Equation 1.

Equation 2.

For example, in Equation 1, if the soft-start time T_SS is selected to be 10 ms, and the EA+ pin is 2.5 V, then the soft-start capacitor C_SS is equal to 82 nF.

7.3.5 Light-Load Power Saving Features

The UCC28950 offers four different light-load management techniques for improving the efficiency of a power converter over a wide load current range.

1. Adaptive Delay,
   1. ADEL, which sets and optimizes the dead-time control for the primary switches over a wide load current range.
   2. ADELEF, which sets and optimizes the delay-time control between the primary side switches and the secondary side switches.
2. TMIN, sets the minimum pulse width as long as the part is not in current limit mode.
3. Dynamic synchronous rectifier on/off control in DCM Mode, For increased efficiency at light loads. The DCM Mode starts when the voltage at CS pin is lower than the threshold set by the user. In DCM Mode, the synchronous output drive signals OUTE and OUTF are brought down low.
4. Burst Mode, for maximum efficiency at very light loads or no load. Burst Mode has an even number of PWM TMIN pulses followed by off time. Transition to the Burst Mode is defined by the TMIN duration set by the user.

7.3.6 Adaptive Delay, (Delay between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))

The resistor R_AB from the DELAB pin, DELAB to GND, along with the resistor divider R_AHI from CS pin to ADEL pin and R_A from ADEL pin to GND sets the delay T_ABSET between one of outputs OUTA or OUTB going low and the other output going high Figure 28. The total resistance of this resistor divider should be in the range between 10 kΩ and 20 kΩ

Figure 28. Delay Definitions Between OUTA and OUTB, OUTC and OUTD

This delay gradually increases as a function of the CS signal from T_ABSET1, which is measured at V_CS = 1.8 V, to T_ABSET2, which is measured at the V_CS = 0.2 V. This approach ensures there will be no shoot-through current during the high-side and low-side MOSFET switching and optimizes the delay for acheiving ZVS condition over a wide load current range. The ratio between the longest and shortest delays is set by the resistor divider R_AHI and R_A. The max ratio is achieved by tying the CS and ADEL pins together. If ADEL is connected to GND, then the delay is fixed, defined only by the resistor R_AB from DELAB to GND. The delay T_CDSET1 and T_CDSET2 settings and their behaviour for outputs OUTC and OUTD are very similar to the one described for OUTA and OUTB. The difference is that resistor R_CD connected between DELCD pin and GND sets the delay T_CDSET. The ratio between the longest and shortest delays is set by the resistor divider R_AHI and R_A.

The delay time T_ABSET is defined by the following Equation 3.

Equation 3.

The same equation is used to define the delay time T_CDSET in another leg except R_AB is replaced by R_CD.

Equation 4.

In these equations R_AB and R_CD are in kΩ and CS, the voltage at pin CS, is in volts and K_A is a numerical coefficient in the range from 0 to 1. The delay time T_ABSET and T_CDSET are in ns, and is measured at the IC pins. These equations are empirical and they are approximated from measured data. Thus, there is no unit agreement in the equations. As an example, assume R_AB = 15 kΩ, CS = 1 V and K_A = 0.5. Then the T_ABSET will be approximately 90 ns. In both Equation 3 and Equation 4, K_A is the same and is defined as:

Equation 5.

K_A sets how the delay varies with the CS pin voltage as shown in Figure 29 and Figure 30.

It is recommended to start by setting K_A = 0 and set T_ABSET and T_CDSET relatively large using equations or plots in this data sheet to avoid hard switching or even shoot through current. The delay between outputs A, B and C, D set by resistors R_AB and R_CS accordingly. Program the optimal delays at light load first. Then by changing K_A set the optimal delay for the outputs A, B at maximum current. K_A for outputs C, D is the same as for A,D. Usually outputs C, D always have ZVS if sufficient delay is provided.

R_A and R_AHI define the portion of voltage at pin CS applied to the pin ADEL (See Figure 48). K_A defines how significantly the delay time depends on CS voltage. K_A varies from 0, where ADEL pin is shorted to ground (R_A = 0) and the delay does not depend on CS voltage, to 1, where ADEL is tied to CS (R_AHI = 0). Setting K_A, R_AB and R_CD provides the ability to maintain optimal ZVS conditions of primary switches over load current because the voltage at CS pin includes the load current reflected to the primary side through the current sensing circuit. The plots in Figure 29 and Figure 30 show the delay time settings as a function of CS voltage and K_A for two different conditions: R_AB = R_CD = 13 kΩ (Figure 29) and R_AB = R_CD = 90 kΩ (Figure 30).

Figure 29. Delay Time Set T_ABSET and T_CDSET
(Over CS voltage variation and selected K_A for R_AB and R_CD equal 13 kΩ)

Figure 30. Delay time set T_ABSET and T_CDSET
(Over CS voltage variation and selected K_A for R_AB and R_CD equal 90 kΩ)

7.3.7 Adaptive Delay (Delay between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF))

The resistor R_EF from the DELEF pin to GND along with the resistor divider R_AEFHI from CS pin to ADELEF pin and R_AEF from ADELEF pin to GND sets equal delays T_AFSET and T_BESET between outputs OUTA or OUTB going low and related output OUTF or OUTE going low Figure 31. The total resistance of this resistor divider should be in the range between 10kΩ and 20kΩ.

Figure 31. Delay Definitions Between OUTA and OUTF, OUTB and OUTE

These delays gradually increase as function of the CS signal from T_AFSET1, which is measured at V_CS = 0.2 V, to T_AFSET2, which is measured at V_CS = 1.8 V. This is opposite to the DELAB and DELCD behavior and this delay is longest (T_AFSET2) when the signal at CS pin is maximized and shortest (T_AFSET1) when the CS signal is minimized. This approach will reduce the synchronous rectifier MOSFET body diode conduction time over a wide load current range thus improving efficiency . The ratio between the longest and shortest delays is set by the resistor divider R_AEFHI and R_AEF. If CS and ADELEF are tied, the ratio is maximized. If ADELEF is connected to GND, then the delay is fixed, defined only by resistor R_EF from DELEF to GND.

The delay time T_AFSET is defined by the following Equation 6. Equation 6 also defines the delay time T_BESET.

Equation 6.

In this equation R_EF is in kΩ, the CS, which is the voltage at pin CS, is in volts and K_EF is a numerical gain factor of CS voltage from 0 to 1. The delay time T_AFSET is in ns, and is measured at the IC pins. This equation is an empirical approximation of measured data, thus, there is no unit agreement in it. As an example, assume R_EF = 15 kΩ, CS = 1 V and K_EF = 0.5. Then the T_AFSET is going to be 41.7 ns. K_EF is defined as:

Equation 7.

R_AEF and R_AEFHI define the portion of voltage at pin CS applied to the pin ADELEF (See Figure 48). K_EF defines how significantly the delay time depends on CS voltage. K_EF varies from 0, where ADELEF pin is shorted to ground (R_AEF = 0) and the delay does not depend on CS voltage, to 1, where ADELEF is tied to CS (R_AEFHI = 0).

The plots in Figure 32 and Figure 33 show delay time settings as function of CS voltage and K_EF for two different conditions: R_EF = 13kΩ (Figure 32) and R_EF = 90kΩ (Figure 33)

Figure 32. Delay Time T_AFSET and T_BESET
(Over CS Voltage and Selected K_EF for R_EF equal 13 kΩ)

Figure 33. Delay Time T_AFSET and T_BESET
(Over CS Voltage and Selected K_EF for R_EF equal 90 kΩ)

7.3.8 Minimum Pulse (TMIN)

The resistor R_TMIN from the TMIN pin to GND sets a fixed minimum pulse width. This pulse is applied to the transformer and enables ZVS at light load. If the output PWM pulse demanded by the feedback loop is shorter than TMIN, then the controller proceeds to burst mode operation where an even number of TMIN pulses are followed by the off time dictated by the feedback loop. The proper selection of the TMIN duration is dictated by the time it takes to raise sufficient magnetizing current in the power transformer to maintain ZVS. The TMIN pulse is measured from the rising edge of OUTA to the falling edge of OUTD – or from the rising edge of OUTB to the falling edge of OUTC. The minimum pulse TMIN is then defined by Equation 8.

Equation 8.

Where TMIN is in ns and R_TMIN is in kΩ The pulse width measured at the transformer will be modified (usually increased) by various propagation and response time delays in the power circuit. Because of the propagation and response time delays in the power circuit, selecting the correct TMIN setting will be an iterative process.

The related plot is shown in Figure 34.

Figure 34. Minimum Time TMIN Over Setting Resistor R_TMIN

The value of minimum duty cycle DMIN is determined by Equation 9.

Equation 9.

Here, F_SW(osc) is oscillator frequency in kHz, TMIN is the minimum pulse in ns and DMIN is in percent.

7.3.9 Burst Mode

If the converter is commanding a duty cycle lower than TMIN, then the controller will go into Burst Mode. The controller will always deliver an even number of Power cycles to the Power transformer. The controller always stops its bursts with an OUTB and an OUTC power delivery cycle. If the controller is still demanding a duty cycle less than TMIN, then the controller goes into shut down mode. Then it waits until the converter is demanding a duty cycle equal or higher than TMIN before the controller puts out TMIN or a PWM duty cycle as dictated by COMP voltage pin.

7.3.10 Switching Frequency Setting

Connecting an external resistor R_T between the RT pin and VREF pins sets the fixed frequency operation and configures the controller as a master providing synchronization output pulses at SYNC pin with 0.5 duty cycle and frequency equal to the internal oscillator. To set the converter in slave mode, connect the external resistor R_T between the RT pin to GND and place an 825-kΩ resistor from the SS pin to GND in parallel with the SS_EN capacitor. This configures the controller as a slave. The slave controller operates with 90° phase shift relative to the master converter if their SYNC pins are tied together. The switching frequency of the converter is equal to the frequency of output pulses. The following Equation 10 defines the nominal switching frequency of the converter configured as a master (resistor R_T between the RT pin and VREF). On the UCC28950 there is an internal clock oscillator frequency which is twice as that of the controller's output frequency.

Equation 10.

In this equation R_T is in kΩ, VREF is in volts and F_SW(nom) is in kHz. This is also an empirical approximation and thus, there is no unit agreement. Assume for example, VREF = 5 V, R_T = 65 kΩ. Then the switching frequency F_SW(nom) is going to be 92.6 kHz.

Equation 11 defines the nominal switching frequency of converter if the converter configured as a slave and the resistor R_T is connected between the RT pin and GND.

Equation 11.

In this equation the R_T is in kΩ, and F_SW(nom) is in kHz. Notice that for VREF = 5 V, Equation 10 and Equation 11 yield the same results.

The plot in Figure 35 shows how F_SW(nom) depends on the resistor R_T value when the VREF = 5 V. As it is seen from Equation 10 and Equation 11, the switching frequency F_SW(nom) is set to the same value for either master or slave configuration provided the same resistor value R_T is used.

Figure 35. Converter Switching Frequency F_SW(nom) Over resistor R_T Value

7.3.11 Slope Compensation (R_SUM)

Slope compensation is needed to prevent a sub-harmonic oscillation in a controller operating in peak current mode (PCM) control or during cycle-by-cycle current limit at duty cycles above 50% (some publications suggest it may happen at D < 50%). Slope compensation in the UCC28950 adds an additional ramp signal to the CS signal and is applied:

• To the PWM comparator in the case of peak current mode control.
• To the input of the cycle-by-cycle comparator.

At low duty cycles and light loads the slope compensation ramp reduces the noise sensitivity of Peak Current Mode control.

Placing a resistor from the R_SUM pin to ground allows the controller to operate in PCM control. Connecting a resistor from R_SUM to VREF switches the controller to voltage mode control (VMC) with the internal PWM ramp. In VMC the resistor at R_SUM provides CS signal slope compensation for operation in cycle-by-cycle current limit. That is, in VMC, the slope compensation is applied only to the cycle-by-cycle comparator while in PCM the slope compensation is applied to both the PWM and cycle-by-cycle current limit comparators. The operation logic of the slope compensation circuit is shown in Figure 36.

Figure 36. The Operation Logic of Slope Compensation Circuit

Too much slope compensation reduces the benefits of PCM control. In the case of cycle-by-cycle current limit, the average current limit becomes lower and this might reduce the start-up capability into large output capacitances.

The optimum compensation ramp varies, depending on duty cycle, L_OUT and L_MAG. A good starting point in selecting the amount of slope compensation is to set the slope compensation ramp to be half the inductor current ramp downslope (inductor current ramp during the off time). The inductor current ramp downslope – as seen at the CS pin input, and neglecting the effects of any filtering at the CS pin, will be:

Equation 12.

Where, V_OUT is the converter’s output voltage of the converter, L_OUT is the output inductor value, a1 is the transformer turns ratio (Np/Ns), CT_RAT is the current transformer ratio (Ip/Is, typically 100:1). Selection of L_OUT, a1 and CT_RAT are described elsewhere in this document. The total slope compensation is 0.5 m₀. Part of this ramp will be due to magnetizing current in the transformer, the rest is added by an appropriately chosen resistor from RSUM to ground.

The slope of the additional ramp, me, added to the CS signal by placing a resistor from RSUM to ground is defined by Equation 13.

Equation 13.

If the resistor from the RSUM pin is connected to the VREF pin, then the controller operates in voltage mode control, still having the slope compensation ramp added to the CS signal used for cycle-by-cycle current limit. In this case the slope is defined by Equation 14.

Equation 14.

In Equation 13 and Equation 14, VREF is in volts, R_SUM is in kΩ and me is in V/μs. These are empirically derived equations without units agreement. As an example, substituting VREF = 5V and R_SUM = 40 kΩ, yields the result 0.125 V/μs. The related plot of me as a function of R_SUM is shown in Figure 37, Because VREF = 5V, the plots generated from Equation 13 and Equation 14 coincide.

Figure 37. Slope of the Added Ramp Over Resistor R_SUM

7.3.12 Dynamic SR ON/OFF Control (DCM Mode)

The voltage at the DCM pin provided by the resistor divider R_DCMHI between VREF pin and DCM, and R_DCM from DCM pin to GND, sets the percentage of 2-V current limit threshold for the Current Sense pin, (CS). If the CS pin voltage falls below the DCM pin threshold voltage, then the controller initiates the light load power saving mode, and shuts down the synchronous rectifiers, OUTE and OUTF. If the CS pin voltage is higher than the DCM pin threshold voltage, then the controller runs in CCM mode. Connecting the DCM pin to VREF makes the controller run in DCM mode and shuts both Outputs OUTE and OUTF. Shorting the DCM pin to GND disables the DCM feature and the controller runs in CCM mode under all conditions.

Figure 38. DCM Functional Block

Figure 39. Duty Cycle Change Over Load Current Change

A nominal 20-µA switched current source is used to create hysteresis. The current source is active only when the system is in DCM Mode. Otherwise, it is inactive and does not affect the node voltage. Therefore, when in the DCM region, the DCM threshold is the voltage divider plus ΔV explained in Equation 15. When in the CCM region, the threshold is the voltage set by the resistor divider. When the CS pin reaches the threshold set on the DCM pin, the system waits to see two consecutive falling edge PWM cycles before switching from CCM to DCM and vice-versa. The magnitude of the hysteresis is a function of the external resistor divider impedance. The hysteresis can be calculated using the following Equation 15:

Equation 15.

Figure 40. Moving from DCM to CCM Mode

Figure 41. Moving from CCM to DCM Mode

DCM must be used in order to prevent reverse current in the output inductor which could cause the synchronous FETS to fail.

The controller must switch to DCM mode at a level where the output inductor current is positive. If the output inductor current is negative when the controller switches to DCM mode then the synchronous FETs will see a large V_DS spike and may fail.

7.3.13 Current Sensing (CS)

The signal from the current sense pin is used for cycle-by-cycle current limit, peak-current mode control, light-load efficiency management and setting the delay time for outputs OUTA, OUTB, OUTC, OUTD and delay time for outputs OUTE, OUTF. Connect the current sense resistor R_CS between CS and GND. Depending on layout, to prevent a potential electrical noise interference, it is recommended to put a small R-C filter between the R_CS resistor and the CS pin.

7.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode

The cycle-by-cycle current limit provides peak current limiting on the primary side of the converter when the load current exceeds its predetermined threshold. For peak current mode control, a certain leading edge blanking time is needed to prevent the controller from false tripping due to switching noise. An internal 30-ns filter at the CS input is provided. The total propagation delay TCS from CS pin to outputs is 100 ns. An external RC filter is still needed if the power stage requires more blanking time. The 2.0-V ±3% cycle-by-cycle current limit threshold is optimized for efficient current transformer based sensing. The duration when a converter operates at cycle-by-cycle current limit depends on the value of soft-start capacitor and how severe the overcurrent condition is. This is achieved by the internal discharge current I_DS Equation 16 and Equation 17 at SS pin.

Equation 16.

Equation 17.

The soft-start capacitor value also determines the so called hiccup mode off-time duration. The behavior of the converter during different modes of operation, along with related soft start capacitor charge/discharge currents are shown in Figure 42.

Figure 42. Timing Diagram of Soft-Start Voltage V_SS

The largest discharge current of 20 µA is when the duty cycle is close to zero. This current sets the shortest operation time during the cycle-by-cycle current limit which is defined as:

Equation 18.

Equation 19.

Thus, if the soft-start capacitor C_SS = 100 nF is selected, then the T_CL(on) time will be 5 ms.

To calculate the hiccup off time T_CL(off) before the restart, the following Equation 20 or Equation 21 needs to be used:

Equation 20.

Equation 21.

With the same soft start capacitor value 100 nF, the off time before the restart is going to be 122 ms. Notice, that if the overcurrent condition happens before the soft start capacitor voltage reaches the 3.7-V threshold during start up, the controller limits the current but the soft start capacitor continues to be charged. As soon as the 3.7-V threshold is reached, the soft-start voltage is quickly pulled up to the 4.65-V threshold by an internal 1-kΩ R_DS(on) switch and the cycle-by-cycle current limit duration timing starts by discharging the soft start capacitor. Depending on specific design requirements, the user can override this default behavior by applying external charge or discharge currents to the soft start capacitor. The whole cycle-by-cycle current limit and hiccup operation is shown in Figure 42. In this example the cycle-by-cycle current limit lasts about 5 ms followed by 122 ms of off time.

Similarly to the overcurrent condition, the hiccup mode with the restart can be overridden by the user if a pullup resistor is connected between the SS and VREF pins. If the pullup current provided by the resistor exceeds 2.5 µA, then the controller remains in the latch off mode. In this case, an external soft-start capacitor value should be calculated with the additional pull-up current taken into account. The latch off mode can be reset externally if the soft-start capacitor is forcibly discharged below 0.55 V or the V_DD voltage is lowered below the UVLO threshold.

7.3.15 Synchronization (SYNC)

The UCC28950 allows flexible configuration of converters operating in synchronized mode by connecting all SYNC pins together and by configuration of the controllers as master and/or slaves. The controller configured as master (resistor between RT and VREF) provides synchronization pulses at the SYNC pin with the frequency equal to 2X the converter frequency F_SW(nom) and 0.5 duty cycle. The controller configured as a slave (resistor between RT and GND and 825-kΩ resistor between SS_EN pin to GND) does not generate the synchronization pulses. The Slave controller synchronizes its own clock to the falling edge of the synchronization signal thus operating 90° phase shifted versus the master converter’s frequency F_SW(nom).

The output inductor in a full bridge converter sees a switching frequency which is twice that seen by the transformer. In the case of the UCC28950 this means that the output inductor operates at 2 x F_SW(nom). This means that the 90° phase shift between master and slave controllers gives a 180° phase shift between the currents in the output inductors and hence maximum ripple cancellation. For more information about synchronizing more than two UCC28950 devices, see Synchronizing Three or More UCC28950 Phase-Shifted, Full-Bridge Controllers, SLUA609.

If the synchronization feature is not used then the SYNC pin may be left floating, but connecting the SYNC pin to GND via a 10-kΩ resistor will reduce noise pickup and switching frequency jitter.

• If any converter is configured as a slave, the SYNC frequency must be greater than or equal to 1.8 times the converter frequency.
• Slave converter does not start until at least one synchronization pulse has been received.
• If any or all converters are configured as slaves, then each converter operates at its own frequency without synchronization after receiving at least one synchronization pulse. Thus, If there is an interruption of synchronization pulses at the slave converter, then the controller uses its own internal clock pulses to maintain operation based on the R_T value that is connected to GND in the slave converter.
• In master mode, SYNC pulses start after SS pin passes its enable threshold which is 0.55 V.
• Slave starts generating SS/EN voltage even though synchronization pulses have not been received.
• It is recommended that the SS on the master controller starts before the SS on the slave controller; therefore SS/EN pin on master converter must reach its enable threshold voltage before SS/EN on the slave converter starts for proper operation. On the same note, it’s recommended that T_MIN resistors on both master and slave are set at the same value.

Figure 43. SYNC_OUT (Master Mode) Timing Diagram

Figure 44. SYNC_IN (Slave Mode) Timing Diagram

7.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)

• All MOSFET control outputs have 0.2-A drive capability.
• The control outputs are configured as P-MOS and N-MOS totem poles with typical R_DS(on) 20 Ω and 10 Ω accordingly.
• The control outputs are capable of charging 100-pF capacitor within 12 ns and discharge within 8 ns.
• The amplitude of output control pulses is equal to V_DD.
• Control outputs are designed to be used with external gate MOSFET/IGBT drivers.
• The design is optimized to prevent the latch up of outputs and verified by extensive tests.

The UCC28950 device has outputs OUTA, OUTB driving the active leg, initiating the duty cycle leg of power MOSFETs in a phase-shifted full bridge power stage, and outputs OUTC, OUTD driving the passive leg, completing the duty cycle leg, as it is shown in the typical timing diagram in Figure 46. Outputs OUTE and OUTF are optimized to drive the synchronous rectifier MOSFETs (Figure 48). These outputs have 200-mA peak-current capabilities and are designed to drive relatively small capacitive loads like inputs of external MOSFET or IGBT drivers. Recommended load capacitance should not exceed 100 pF. The amplitude of the output signal is equal to the V_DD voltage.

7.3.17 Supply Voltage (VDD)

Connect this pin to a bias supply in the range from 8 V to 17 V. Place high quality, low ESR and ESL, at least 1-µF ceramic bypass capacitor C_VDD from this pin to GND. It is recommended to use a 10-Ω resistor in series from the bias supply to the VDD pin to form an RC filter with the C_VDD capacitor.

7.3.18 Ground (GND)

All signals are referenced to this node. It is recommended to have a separate quiet analog plane connected in one place to the power plane. The analog plane connects the components related to the pins VREF, EA+, EA-, COMP, SS/EN, DELAB, DELCD, DELEF, TMIN, RT, RSUM. The power plane connects the components related to the pins DCM, ADELEF, ADEL, CS, SYNC, OUTF, OUTE, OUTD, OUTC, OUTB, OUTA, and VDD. An example of layout and ground planes connection is shown in Figure 45.

Figure 45. Layout Recommendation for Analog and Power Planes