8.3.1.5 SYNC

This pin is a bi-directional synchronization terminal. This pin should be left open if not used.

This pin provides an input for an external-clock signal which synchronizes the internal oscillator of the UCC2897A controller. The synchronizing frequency must be higher than the free-running frequency of the onboard oscillator (T_SYNC < T_SW). The acceptable minimum pulse-width of the synchronization signal is approximately 50 ns (positive logic), and should remain shorter than Equation 6.

If the pulse-width of the synchronization signal stays within these limits, the maximum-operating duty ratio remains valid as defined by the ratio of RON and ROFF, and DMAX is the same in free-running and in synchronized modes of operation. If the pulse width of the synchronization signal would exceed the (1 – D_MAX) × T_SYNC limit, the maximum-operating duty cycle is defined by the synchronization pulse width.

In the stand-alone mode, the sync pin is driven by the internal oscillator which provides output pulses. The pulse width from SYNC output does not vary with the duty cycle. That signal synchronizes other PWM controllers or circuits requiring a constant-frequency time base.

External capacitance should be minimized on this pin layout. Capacitors are not connected between SYNC and GND or PGND. For more information on synchronization of the UCC2897A refer to the section of this datasheet.