SLUSFA6 October 2023 UCC44273
PRODUCTION DATA
The UCC44273 single-channel, high-speed, low-side gate-driver device is capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, the UCC44273 device is capable of sourcing and sinking high peak-current pulses into capacitive loads offering rail-to-rail drive capability and extremely small propagation delay of 13 ns (typical). The UCC44273 provides 4-A source, 4-A sink (symmetrical drive) peak-drive current capability. The device is designed to operate over a wide VDD range of 4.5 to 18 V, and a wide temperature range of –40°C to 140°C. Internal undervoltage lockout (UVLO) circuitry on the VDD pin holds the output low outside VDD operating range. The capability to operate at low voltage levels, such as below 5 V, along with best-in- class switching characteristics, is especially suited for driving emerging wide bandgap power-switching devices such as GaN power-semiconductor devices.
The input pin threshold of the UCC44273 device is based on TTL and CMOS-compatible low-voltage logic which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.
| PART NUMBER | PACKAGE | PEAK CURRENT (SOURCE, SINK) | INPUT THRESHOLD LOGIC |
|---|---|---|---|
| UCC44273 | SOT-23, 5 pin | 4-A, 4-A (Symmetrical Drive) | CMOS and
TTL-Compatible (low voltage, independent of VDD bias voltage) |
| FEATURE | BENEFIT |
|---|---|
| High Source, Sink Current Capability 4 A, 4 A (Symmetrical) | High current capability offers flexibility in employing the UCC44273 to drive a variety of power switching devices at varying speeds |
| Best-in-class 13-ns (typ) Propagation delay | Extremely low-pulse transmission distortion |
| Expanded VDD Operating range of 4.5 V to 18 V | Flexibility in system design Low VDD operation ensures compatibility with emerging wide-bandgap power devices such as GaN |
| Expanded Operating Temperature range of
–40°C to 140°C (See Recommended Operating Conditions table) | |
| VDD UVLO Protection | Outputs are held low in UVLO condition, which ensures predictable glitch-free operation at power up and power down |
| Output held low when input pin (IN) in floating condition | Protection feature, especially useful in passing abnormal condition tests during protection certification |
| Ability of input pin to handle voltage levels not restricted by VDD pin bias voltage | System simplification, especially related to auxiliary bias supply architecture |
| CMOS and TTL compatible input threshold logic with wide hysteresis in UCC44273 | Enhanced noise immunity, while retaining compatibility with microcontroller logic-level input signals (3.3 V, 5 V) optimized for digital power |
| Ability to handle –5 VDC at input pins | Increased robustness in noisy environments |