8.3.2 Input Stage

The input pin of UCC5304 is based on a TTL and CMOS compatible input-threshold logic that is totally isolated from the VDD supply voltage. The input pins are easy to drive with logic-level control signals (such as those from 3.3-V micro-controllers), since the UCC5304 has a typical high threshold (V_INAH) of 1.8 V and a typical low threshold of 1 V, which vary little with temperature (see and ). A wide hysterisis (V_{INA_HYS}) of 0.8 V makes for good noise immunity and stable operation. If the input is ever left open, an internal pull-down resistor forces the pin low. This resistance is typically 200 kΩ (see Functional Block Diagram).

Since the input side of UCC5304 is isolated from the output drivers, the input signal amplitude can be larger or smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows greater flexibility when integrating with control signal sources, and allows the user to choose the most efficient VDD for their MOSFET/IGBT gate. That said, the amplitude of any signal applied to IN must not exceed VCCI.