The total loss, P_G, in the gate-driver subsystem includes the power losses (P_GD) of the UCC5350-Q1 device and the power losses in the peripheral circuitry, such as the external gate-drive resistor.

The P_GD value is the key power loss which determines the thermal safety-related limits of the UCC5350-Q1 device, and it can be estimated by calculating losses from several components.

The first component is the static power loss, P_GDQ, which includes quiescent power loss on the driver as well as driver self-power consumption when operating with a certain switching frequency. The P_GDQ parameter is measured on the bench with no load connected to the OUT pins at a given V_CC1, V_CC2, switching frequency, and ambient temperature. In this example, V_CC1 is 3.3V and V_CC2 is 18 V. The current on each power supply, with PWM switching from 0 V to 3.3 V at 150 kHz, is measured to be I_CC1 = 1.67 mA and I_CC2 = 1.11 mA . Therefore, use Equation 5 to calculate P_GDQ.

Equation 5.

The second component is the switching operation loss, P_GDO, with a given load capacitance which the driver charges and discharges the load during each switching cycle. Use Equation 6 to calculate the total dynamic loss from load switching, P_GSW.

Equation 6.

where

• Q_G is the gate charge of the power transistor at V_CC2.

So, for this example application the total dynamic loss from load switching is approximately 340 mW as calculated in Equation 7.

Equation 7.

Q_G represents the total gate charge of the power transistor and is subject to change with different testing conditions. The UCC5350-Q1 gate-driver loss on the output stage, P_GDO, is part of P_GSW. P_GDO is equal to P_GSW if the external gate-driver resistance and power-transistor internal resistance are 0 Ω, and all the gate driver-loss will be dissipated inside the UCC5350-Q1. If an external turn-on and turn-off resistance exists, the total loss is distributed between the gate driver pull-up/down resistance, external gate resistance, and power-transistor internal resistance. Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 10 A, however, it will be non-linear if the source/sink current is saturated. The gate driver loss will be estimated in the case in which it is not saturated as given in Equation 8.

In this design example, all the predicted source and sink currents are less than 10 A, therefore, use Equation 9 to estimate the gate-driver loss.

Equation 9.

where

• V_OUTH/L(t) is the gate-driver OUT pin voltage during the turnon and turnoff period. In cases where the output is saturated for some time, this value can be simplified as a constant-current source (10 A at turnon and turnoff) charging or discharging a load capacitor. Then, the V_OUTH/L(t) waveform will be linear and the T_{R_Sys} and T_{F_Sys} can be easily predicted.

Use Equation 10 to calculate the total gate-driver loss dissipated in the UCC5350-Q1 gate driver, P_GD.

Equation 10.