ZHCSKG7B June 2019 – February 2024 UCC5390-Q1
PRODUCTION DATA
The input pins (IN+ and IN–) of the UCC5390-Q1 are based on CMOS-compatible input-threshold logic that is completely isolated from the VCC2 supply voltage. The input pins are easy to drive with logic-level control signals (such as those from 3.3-V microcontrollers), because the UCC5390-Q1 has a typical high threshold (VIT+(IN)) of 0.55 × VCC1 and a typical low threshold of 0.45 × VCC1. A wide hysteresis (Vhys(IN)) of 0.1 × VCC1 makes for good noise immunity and stable operation. If either of the inputs are left open, 128 kΩ of internal pull-down resistance forces the IN+ pin low and 128 kΩ of internal resistance pulls IN– high. However, TI still recommends grounding an input or tying to VCC1 if it is not being used for improved noise immunity.
Because the input side of the UCC5390-Q1 is isolated from the output driver, the input signal amplitude can be larger or smaller than VCC2 provided that it does not exceed the recommended limit. This feature allows greater flexibility when integrating the gate-driver with control signal sources and allows the user to choose the most efficient VCC2 for any gate. However, the amplitude of any signal applied to IN+ or IN– must never be at a voltage higher than VCC1.