米6体育平台手机版

SLUSFL3B June 2024 – October 2024 UCC57102 , UCC57108

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

5.6 Switching Characteristics

VDD = 15 V, VEE = 0 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VEE to GND, TJ = –40°C to +150°C, CL = 0 pF, unless otherwise noted. ⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_RA,t_RB	Output Rise Time	C_L=1.8nF, 10% to 90%, Vin = 0 to 3.3V		8	18	ns
t_FA,t_FB	Output Fall Time	C_L=1.8nF, 90% to 10%, Vin = 0 to 3.3V		14	32	ns
t_D2	Propagation Delay – Input falling to output falling	C_L=1.8nF, from 1V falling on Vin to 90% of output fall, Vin=0 - 3.3V, Fsw=500kHz, 50% duty cycle		28	50	ns
t_D1	Propagation Delay – Input rising to output rising	C_L=1.8nF, from 2V rising on Vin to 10% of output rise, Vin=0 - 3.3V, Fsw=500kHz, 50% duty cycle		26	50	ns
t_{PD_EN}	EN Response Delay (W Version)	C_L=1.8nF, from 2V rising on EN to 10% of output rise, EN=0 - 3.3V, Fsw=500kHz, 50% duty cycle		26	40	ns
t_{PD_DIS}	DIS Response Delay (W Version)	C_L=1.8nF, from 1V falling on EN to 90% of output fall, EN=0 - 3.3V, Fsw=500kHz, 50% duty cycle		27	45	ns
t_PWmin	Minimum Input Pulse Width That Passes to Output	C_L=1.8nF, Vin=0 - 3.3V, Fsw=500kHz, Vo >2V		9	15	ns
t_PWD	Pulse Width Distortion	Input Pulse Width = 100ns, 500kHz t_D2 – t_D1,C_L=1.8nF	-10		10	ns

(1) Switching parameters are not tested in production.