The Active Miller clamp function (CLAMP output) is used to prevent the power transistor from false turn-on due Miller capacitance induced current. The active Miller clamp adds a low impedance path between power transistor gate terminal and VEE2 to pull the gate of the external FET hard to VEE2, bypassing any external gate resistors. The Miller clamp engages when the OUTH voltage falls below the V_CLPTH, which is selected using the CFG5[MCLPTH] bits (CFG5). Additionally, the Miller clamp is enabled/disabled using the CFG4[MCLP_DIS] bit (CFG4). The status of the Miller clamp is available in the STATUS3[MCLP_STATE] bit (STATUS3).

If additional pulldown strength is required, the CLAMP output is configured to drive an external Miller clamp FET. Use the CFG4[MCLP_CFG] bit to select between the internal and external Miller clamp (CFG4). This option can be configured through the register. The implementation block diagram and timing scheme are shown in Figure 7-13 and Figure 7-15 respectively.

Figure 7-13 Block diagram of implementation of internal Miller clamp function.

Figure 7-14 Block diagram of implementation of external Miller clamp function.

Figure 7-15 Timing scheme of implementation of Miller clamp function.