UVLO functions are implemented for all three gate driver power supplies VCC1, VCC2, and VEE2. The VCC1 UVLO/OVLO ensures a valid supply is connected for the required logic interface. The UVLO/OVLO for VCC2 and VEE2 ensures valid supplies based on the type of transistor used. The UVLO function prevents overheating damage to the IGBTs/MOSFETs from being under-driven. The OVLO functions are implemented to prevent gate oxide degradation (shortened lifetime) of the IGBTs/MOSFETs from an over-voltage supply at turned on. The device powers up when a valid VCC1 supply (V_IT+(UVLO1) < V_VCC1 < V_IT+(OVLO1)) and non-UV VCC2 supply (V_VCC2 > V_IT+(UVLO2)) are connected. The driver outputs are high impedance until the valid supplies are connected and the internal supplies are in regulation. While the driver output is high impedance, the output to the gate of the external power switch is held low with a passive and active pulldown circuit. See the Section 7.3.5.2 section for more details. Once valid supplies are connected and internal supplies are valid, the output state is determined by the Enable/Disable Driver command any fault conditions that exist. SPI communication is unavailable while VCC1 is lower than the UVLO1 threshold.

The OVLO and UVLO functions are enabled/disabled using the following bits: CFG1[UV1_DIS] for VCC1 UVLO, CFG1[OV1_DIS] for VCC1 OVLO, CFG4[UV2_DIS] for VCC2 UVLO,CFG4[OV2_DIS] for VCC2 OVLO, and CFG4[UVOV3_EN] for both the OVLO and UVLO for VEE2. The UVLO and OVLO thresholds for VCC1, VCC2 and VEE2 are programmable in order to customize the driver for different types of power transistors. Use the CFG1[UVLO1_LEVEL] and CFG1[OVLO1_LEVEL] (for VCC1), CFG7[UVLO2TH] and CFG7[OVLO2TH] (for VCC2), and CFG7[UVLO3TH] and CFG7[IOVLO3TH] (for VEE2) bits to set the desired threshold. See CFG1 and CFG7.

The fault status for the OVLO and UVLO function are located in STATUS2[UVLO1_FAULT] for VCC1 UVLO, STATUS2[OVLO1_FAULT] for VCC1 OVLO, STATUS3[UVLO2_FAULT] for VCC2 UVLO, STATUS3[OVLO2_FAULT] for VCC2 OVLO, STATUS3[UVLO3_FAULT] for VEE2 UVLO, and STATUS3[OVLO3_FAULT] for VEE2 OVLO. See STATUS2 and STATUS3 for additional details. The timing diagrams for the VCC1 and VCC2 UVLO and OVLO functions are shown in and Figure 7-10, respectively. The VEE2 timing diagram is shown in Figure 7-11.

Figure 7-9 Illustration of UVLO and OVLO timing schemes of VCC1.

Figure 7-10 Illustration of UVLO and OVLO timing schemes of VCC2

Figure 7-11 Illustration of UVLO and OVLO timing schemes of VEE2