Upon receiving a valid DRV_EN command, the device transitions to the Active state. In this state, the STATUS2[DRV_EN_RCVD] bit (STATUS2) is set to '1', the CRC for the configuration registers is calculated and stored, SPI writes to most registers are disabled, and the driver outputs are enabled to follow the IN+/IN- inputs, assuming there is no fault condition. All of the registers are Read Only, with the exception of CONTROL2[CLR_STAT_REG], CFG8[IOUT_SEL], and CFG8[CRC_DIS]. Any writes to any other registers/ bits are ignored. The device remains in Active mode until the SW_RESET command is sent, a DRV_DIS command followed by a CONFIG_IN is sent, or a primary side thermal shutdown fault occurs. The SW_RESET command disables the driver and resets all registers except for the driver address, while the DRV_DIS command disables the driver while leaving the register contents intact.