The device integrates clock monitor functions to identify clock faults during operation. The Clock monitor detects internal oscillator failures:

• Oscillator clock stuck high or stuck low
• Clock frequency is out of range ±30%

The clock monitor is enabled during a power-up event after the power-on reset is released. The clocks on the primary side and secondary side are monitored. In the event of a clock fault on the primary side, the STATUS4[CLK_MON_SEC_FAULT] bit (STATUS4) is set, the driver is forced to the state determined by the CFG11[FS_STATE_CLK_MON_SEC_FAULT] bit (CFG11) and, if unmasked, the nFLT1 output pulls low. In the event of a clock fault on the secondary side, the STATUS2[CLK_MON_PRI_FAULT] bit (STATUS2) is set, and, if unmasked, the nFLT1 output pulls low. The secondary side clock monitor has no effect on the gate driver output state.