The integrity of the PWM channel is monitored end to end using two checks. The first check monitors the communication across the isolation channel. The received state on the secondary side is communicated back o the primary side to ensure the two match. If there is a mismatch between the IN+ state and the received IN+ state, the STATUS1[PWM_COMP_CHK_FAULT] bit (STATUS1) is set, if unmasked, nFLT1 pulls low, and the driver output is forced ot the state defined by CFG3[FS_STATE_PWM_CHK] (CFG3). The second check monitors the actual gate voltage of the power transistor to ensure the gate is in the correct state. The monitored gate voltage is first converted to logic state and indicated in the STATUS3[GM_STATE] bit (STATUS3). The converted gate voltage logic state is then compared with the input PWM (IN+) signal. The mismatch of the two signals causes a gate voltage monitor fault condition where the STATUS3[GM_FAULT] bit (STATUS3) is set, the driver output is forced to the state defined by CFG10[FS_STATE_GM] (CFG10), and, if unmasked, nFLT1 pulls low. Blanking time relative to the driver outputs is used to prevent false reporting of the gate voltage monitor error during driver transitions. During 2LTOFF transitions, the blanking time starts after the 2LTOFF plateau timer expires in order to prevent false GM faults during the transition. Alternatively, the GM fault may be disabled during STO and 2LTOFF using the CFG5[GM_STO2LTO_DIS] bit (CFG5). The blanking time is adjustable using the CFG4[GM_BLK] bits (CFG4). Additionally, the gate monitoring function may be disabled entirely using the CFG4[GM_EN] bit (CFG4). The implementation block diagram and timing schemes are presented in Figure 7-31 and Figure 7-32.

Figure 7-31 Block diagram of implementation of gate voltage monitor function.

Figure 7-32 Timing scheme of implementation of gate voltage monitor function.