The SDO CRC checksum is continuously calculated as data is clocked out of SDO. The resulting CRC is stored in the CRCDATA[CRC_RX] bits. The bits are updated whenever nCS transitions from low to high. The CRC calculation logic is reset (reset value = 0xFF) when the CRC_RX bits are read or when the CONTROL1[CLR_SPI_CRC] bit is written. Note that the CRC_RX bits are reset immediately with the read, and the next CRC_RX value begins its calculation while clocking out of the CRC_RX bits. This means the received CRC_RX must be included in the next CRC calculation (i.e. the received CRC_RX is the first byte to be xor'd with the 0xFF reset value).