The clock monitor circuit integrates a diagnostic that checks the integrity of the monitoring circuit. The diagnostic is run automatically during the startup process. Additionally, a simulated clock monitor fault is generated by writing the CONTROL1[CLK_MON_CHK_PRI] bit (Figure 7-72) for the primary side and the CONTROL2[CLK_MON_CHK_SEC] bit (Figure 7-73) for the secondary side. When enabled, the enabled diagnostics emulates clock failure that causes a clock monitor fault. During this self-test, the actual oscillator frequency is not changed.