ZHCSMR1C october   2019  – september 2021 UCC5870-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Electrical Characteristics
    8. 6.8  SPI Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supplies
        1. 7.3.1.1 VCC1
        2. 7.3.1.2 VCC2
        3. 7.3.1.3 VEE2
        4. 7.3.1.4 VREG1
        5. 7.3.1.5 VREG2
        6. 7.3.1.6 VREF
        7. 7.3.1.7 Other Internal Rails
      2. 7.3.2 Driver Stage
      3. 7.3.3 Integrated ADC for Front-End Analog (FEA) Signal Processing
        1. 7.3.3.1 AI* Setup
        2. 7.3.3.2 ADC Setup and Sampling Modes
          1. 7.3.3.2.1 Center Sampling Mode
          2. 7.3.3.2.2 Edge Sampling Mode
          3. 7.3.3.2.3 Hybrid Mode
        3. 7.3.3.3 DOUT Functionality
      4. 7.3.4 Fault and Warning Classification
      5. 7.3.5 Diagnostic Features
        1. 7.3.5.1  Undervoltage Lockout (UVLO) and Overvoltage Lockout (OVLO)
          1. 7.3.5.1.1 Built-In Self Test (BIST)
            1. 7.3.5.1.1.1 Analog Built-In Self Test (ABIST)
            2. 7.3.5.1.1.2 Function BIST
            3. 7.3.5.1.1.3 Clock Monitor
              1. 7.3.5.1.1.3.1 Clock Monitor Built-In Self Test
        2. 7.3.5.2  CLAMP, OUTH, and OUTL Clamping Circuits
        3. 7.3.5.3  Active Miller Clamp
        4. 7.3.5.4  DESAT based Short Circuit Protection (DESAT)
        5. 7.3.5.5  Shunt Resistor based Overcurrent Protection (OCP) and Short Circuit Protection (SCP)
        6. 7.3.5.6  Temperature Monitoring and Protection for the Power Transistors
        7. 7.3.5.7  Active High Voltage Clamping (VCECLP)
        8. 7.3.5.8  Two-Level Turn-Off
        9. 7.3.5.9  Soft Turn-Off (STO)
        10. 7.3.5.10 Thermal Shutdown (TSD) and Temperature Warning (TWN) of Driver IC
        11. 7.3.5.11 Active Short Circuit Support (ASC)
        12. 7.3.5.12 Shoot-Through Protection (STP)
        13. 7.3.5.13 Gate Voltage Monitoring and Status Feedback
        14. 7.3.5.14 VGTH Monitor
        15. 7.3.5.15 Cyclic Redundancy Check (CRC)
          1. 7.3.5.15.1 Calculating CRC
        16. 7.3.5.16 Configuration Data CRC
        17. 7.3.5.17 SPI Transfer Write/Read CRC
          1. 7.3.5.17.1 SDI CRC Check
          2. 7.3.5.17.2 SDO CRC Check
        18. 7.3.5.18 TRIM CRC Check
    4. 7.4 Device Functional Modes
      1. 7.4.1 State 1: RESET
      2. 7.4.2 State 2: Configuration 1
      3. 7.4.3 State 3: Configuration 2
      4. 7.4.4 State 4: Active
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 System Configuration of SPI Communication
          1. 7.5.1.1.1 Independent Slave Configuration
          2. 7.5.1.1.2 Daisy Chain Configuration
          3. 7.5.1.1.3 Address-based Configuration
        2. 7.5.1.2 SPI Data Frame
          1. 7.5.1.2.1 Writing a Register
          2. 7.5.1.2.2 Reading a Register
    6. 7.6 Register Maps
      1. 7.6.1 UCC5870 Registers
  8. 8 Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Dissipation Considerations
      2. 8.1.2 Device Addressing
    2. 8.2 Typical Application Using Internal ADC Reference and Power FET Sense Current Monitoring
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VCC1, VCC2, and VEE2 Bypass Capacitors
        2. 8.2.2.2 VREF, VREG1, and VREG2 Bypass Capacitors
        3. 8.2.2.3 Bootstrap Capacitor (VBST)
        4. 8.2.2.4 VCECLP Input
        5. 8.2.2.5 External CLAMP Output
        6. 8.2.2.6 AI* Inputs
        7. 8.2.2.7 OUTH/ OUTL Outputs
        8. 8.2.2.8 nFLT* Outputs
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application Using DESAT Power FET Monitoring
      1. 8.3.1 Detailed Design Procedure
        1. 8.3.1.1 DESAT Input
      2. 8.3.2 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 VCC1 Power Supply
    2. 9.2 VCC2 Power Supply
    3. 9.3 VEE2 Power Supply
    4. 9.4 VREF Supply (Optional)
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Component Placement
      2. 10.1.2 Grounding Considerations
      3. 10.1.3 High-Voltage Considerations
      4. 10.1.4 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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订购信息

7.5.1.2 SPI Data Frame

The SPI data frame is composed of 16bits. The timing scheme and format of a data frame is shown in Figure 7-43 and Figure 7-44.

GUID-FD1B7C5F-CA6A-4CAD-8DF7-41960D08F453-low.pngFigure 7-43 Timing scheme of SPI communication
GUID-B814A9C7-96F5-4C5E-B693-36695853E33E-low.pngFigure 7-44 16-bit of SPI data frame.

The 16-bit data frame includes three data fields: chip address (CHIP_ADDR), command type (CMD), and an 8-bit data (DATA). The chip address (CHIP_ADDR) bits are used, regardless of the system configuration. However, when using the Daisy Chain or Independent Slave configurations, 0x0 or 0xF is used for all of the devices in the system. In Address-based configuration, the devices are individually addressed, and all devices respond to 0x0 and 0xF. Note that SDO is high impedance until it receives a command with the programmed device address. Once receiving the valid addressed command, the SDO is driven to send out data. When an invalid addressed command or 0xF (broadcast address) is received, the SDO returns to high impedance, thereby allowing other devices to take control of the shared MISO (SDO) bus. There are 10 command types used by the device, defined in Table 7-3.

Table 7-3 SPI message commands
16-BIT DATA FRAME
BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Command Name Command Description CHIP_ADDR CMD + DATA
DRV_EN Driver output enable CA[3] CA[2] CA[1] CA[0] 0 0 0 0 0 0 0 0 1 0 0 1
DRV_DIS Driver output disable CA[3] CA[2] CA[1] CA[0] 0 0 0 0 0 0 0 0 1 0 1 0
RD_DATA Read data from register address RA[4:0] CA[3] CA[2] CA[1] CA[0] 0 0 0 1 0 0 0 RA[4] RA[3] RA[2] RA[1] RA[0]
CFG_IN Enter configuration state CA[3] CA[2] CA[1] CA[0] 0 0 1 0 0 0 1 0 0 0 1 0
NOP No operation CA[3] CA[2] CA[1] CA[0] 0 1 0 1 0 1 0 0 0 0 1 0
SW_RESET Software RESET (Reinitialize the configurable registers) CA[3] CA[2] CA[1] CA[0] 0 1 1 1 0 0 0 0 1 0 0 0
WRH Write D[15:8] to register RA[4:0] CA[3] CA[2] CA[1] CA[0] 1 0 1 0 D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]
WRL Write D[7:0] to register RA[4:0] CA[3] CA[2] CA[1] CA[0] 1 0 1 1 D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
WR_RA Write register address RA[4:0] CA[3] CA[2] CA[1] CA[0] 1 1 0 0 0 0 0 RA[4] RA[3] RA[2] RA[1] RA[0]
WR_CA(1) Write chip address CA[3:0] 1 1 1 1 1 1 0 1 1 0 1 0 CA[3] CA[2] CA[1] CA[0]
(1) IN+ must be high to program CHIP address
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