Ideally, the ARM core should begin execution of ROM code only after V33>3V. The ROM code reads trim values and loads trim registers. Lack of sufficient voltage during this operation can result in unexpected device functioning. Depending on V33 slew rate, the duration for which there is insufficient voltage on V33 is varied. During this time, a reliable trim operation is not ensured. Applying an RC filter between V33 and the RESET pin can increase the delay from V33 power up to the device coming out of reset.

Figure 11-2 Recommended Timing Diagram of V33 and RESET for UCD3138 and UCD3138064

Example Solution:

If the V33 supply slew rate is 0.6 V/ms, then the minimum τ required is calculated as follows:

Equation 2.

Equation 3.

If R and C are 2.21 k and 2.2 uF, then τ evaluates as:

Equation 4.

These values of 2.21 kΩ and 2.2 µF will ensure that the RESET will be a logic-0 until V33 crosses 3V. [τ > τRESET_MIN]