米6体育平台手机版

ZHCSAY5D march 2013 – april 2021 UCD3138064

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

RJA|40
- MPQF467A
RMH|40
- MPQF388A
RGC|64
- MPQF125F

散热焊盘机械数据 (封装 | 引脚)

RJA|40
- QFND826
RGC|64
- QFND102O

订购信息

8.5 Electrical Characteristics

V33A = V33D = V33DIO = 3.3 V; 1μF from BP18 to DGND, T_J = –40 °C to 125 °C (unless otherwise noted)

PARAMETER		TEST CONDITION	MIN	TYP	MAX	UNIT
SUPPLY CURRENT
	I33A	Measured on V33A. The device is powered up but all ADC12 and EADC sampling is disabled		6.3		mA
	I33DIO	All GPIO and communication pins are open		0.35		mA
	I33D	ROM program execution		60		mA
	I33D ⁽⁵⁾	Flash programming in ROM mode			70	mA
	I33	The device is in ROM mode with all DPWMs enabled and switching at 2 MHz. The DPWMs are all unloaded.			100	mA
ERROR ADC INPUTS EAP, EAN
	EAP – AGND		–0.15		1.998	V
	EAP – EAN		–0.256		1.848	V
	Typical error range	AFE = 0	–256		248	mV
	EAP – EAN Error voltage digital resolution	AFE = 3	0.8	1	1.20	mV
		AFE = 2	1.7	2	2.30	mV
		AFE = 1	3.55	4	4.45	mV
		AFE = 0	6.90	8	9.10	mV
R_EA	Input impedance (See Figure 9-1)	AGND reference	0.5			MΩ
I_OFFSET	Input offset current (See Figure 9-1)		–5		5	μA
	EADC Offset	Input voltage = 0 V at AFE = 0	–2		2	LSB
		Input voltage = 0 V at AFE = 1	–2.5		2.5	LSB
		Input voltage = 0 V at AFE = 2	–3		-3	LSB
		Input voltage = 0 V at AFE = 3	–4		4	LSB
	Sample Rate				15.625	MHz
	Analog Front End Amplifier Bandwidth			100		MHz
A₀	Gain	See Figure 9-2		1		V/V
A₀	Minimum output voltage				21	mV
EADC DAC
	DAC range		0		1.6	V
	VREF DAC reference resolution	10-bit, No dithering enabled		1.56		mV
	VREF DAC reference resolution	With 4-bit dithering enabled		97.6		μV
	INL		–2.0		2.0	LSB
	DNL	Does not include MSB transition	–1.0		2.1	LSB
	DNL at MSB transition			–1.4		LSB
	DAC reference voltage		1.58		1.61	V
ADC12
I_BIAS	Bias current for PMBus address pins		9.5		10.5	μA
	Measurement range for voltage monitoring		0		2.5	V
	Internal ADC reference voltage	–40 to 125 °C	2.475	2.500	2.53	V
	Change in Internal ADC reference from 25°C reference voltage ⁽⁵⁾	–40 to 25 °C		–0.7		mV
		25 to 125 °C		–2.1		mV
	ADC12 INL integral nonlinearity ⁽⁵⁾	ADC_SAMPLING_SEL = 6 for all ADC12 data, 25 to 125 °C		–7.5/+2.9		LSB
	ADC12 DNL differential nonlinearity ⁽⁵⁾			–0.7/+3.2		LSB
	ADC Zero Scale Error		–7		7	mV
	ADC Full Scale Error		–35		35	mV
	Input bias	2.5 V applied to pin			200	nA
	Input leakage resistance ⁽⁵⁾	ADC_SAMPLING_SEL= 6 or 0		1		MΩ
	Input Capacitance ⁽⁵⁾			10		pF
DIGITAL INPUTS/OUTPUTS⁽¹⁾⁽²⁾
V_OL	Low-level output voltage⁽³⁾	I_OH = 4 mA, V33DIO = 3 V			DGND + 0.25	V
V_OH	High-level output voltage ⁽³⁾	I_OH = –4 mA, V33DIO = 3 V	V33DIO – 0.6			V
V_IH	High-level input voltage	V33DIO = 3 V	2.1			V
V_IL	Low-level input voltage	V33DIO = 3 V			1.1	V
I_OH	Output sinking current				4	mA
I_OL	Output sourcing current		–4			mA
SYSTEM PERFORMANCE
TWD	Watchdog time out resolution	Total time is: TWD x (WDCTRL.PERIOD+1)	13.1	17	22.7	ms
	Processor master clock (MCLK)			31.25		MHz
t_Delay	Digital filter delay⁽⁴⁾	(1 clock = 32 ns)			6	MCLKs
	Retention period of flash content (data retention and program)	T_J = 25 °C	100			years
f_(PCLK)	Internal oscillator frequency		240	250	260	MHz
	Flash Read			1		MCLKs
I_SHARE	Current share current source (See Section 9.3.15)		238		259	μA
R_SHARE	Current share resistor (See Section 9.3.15)		9.75		10.3	kΩ
POWER ON RESET AND BROWN OUT (V33A pin, See Figure 8-3)
VGH		Voltage Good High		2.7		V
VGL		Voltage Good Low		2.5		V
V_res	Voltage at which IReset signal is valid⁽⁵⁾			0.8		V
	Brownout	Internal signal warning of brownout conditions		2.9		V
TEMPERATURE SENSOR⁽⁵⁾
V_TEMP		Voltage range of sensor	1.46		2.44	V
	Voltage resolution	Volts/°C		5.9		mV/°C
	Temperature resolution	Degree C per bit		0.1034		°C/LSB
	Accuracy⁽⁵⁾⁽⁶⁾	–40 to 125 °C	–10	±5	10	°C
	Temperature range	–40 to 125 °C	–40		125	°C
I_TEMP		Current draw of sensor when active		30		μA
V_AMB	Ambient temperature	Trimmed 25 °C reading		1.85		V
ANALOG COMPARATOR
DAC	Reference DAC Range		0		2.5	V
	Reference Voltage		2.478	2.5	2.513	V
	Bits			7		bits
	INL⁽⁵⁾		–0.42		0.21	LSB
	DNL⁽⁵⁾		0.06		0.12	LSB
	Offset		–5.5		19.5	mV
	Reference DAC buffered output load⁽⁷⁾		–0.5		1	mA
	Buffer offset (–0.5 mA)		4.6		8.3	mV
	Buffer offset (1.0 mA)		–0.05		17	mV
	Output Range (–0.5 mA)		0.2		2.5	V
	Output Range (1.0 mA)		0		2.5	V

(1) DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.

(2) On the 40 pin package V33DIO is connected to V33D internally.

(3) The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. Maximum sink current per pin = –6 mA at V_OL; maximum source current per pin = 6 mA at V_OH.

(4) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which has no variation associated with it, must be accounted for when calculating the system dynamic response.

(5) Characterized by design and not production tested.

(6) Ambient temperature offset value should be used from the TEMPSENCTRL register to meet accuracy.

(7) Available from reference DACs for comparators D, E, F and G.