ZHCSAY5D march 2013 – april 2021 UCD3138064
PRODUCTION DATA
DPWM1 is synchronized to DPWM0, DPWM2 is synchronized to DPWM1, and DPWM3 is synchronized to DPWM2, ½ period out of phase using these commands:
Dpwm1Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; //configured to slave Dpwm2Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave Dpwm3Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave | ||
Dpwm0Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC; Dpwm1Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC; Dpwm2Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC; | ||
LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_SEL = 0; LoopMuxRegs.DPWMMUX.bit.DPWM2_SYNC_SEL = 1; LoopMuxRegs.DPWMMUX.bit.DPWM3_SYNC_SEL = 2; | // Slave to dpwm-0 // Slave to dpwm-1 // Slave to dpwm-2 |
If the event registers on the DPWMs are the same, the two pairs of signals will be symmetrical. All code examples are taken from the PSFB EVM code, unless otherwise stated.