ZHCSER5
December 2015
UCD3138064A
PRODUCTION DATA.
1
器件概述
1.1
特性
1.2
应用范围
1.3
说明
1.4
功能方框图
2
修订历史记录
3
Device Options
3.1
Device Comparison Table
3.2
Product Selection Matrix
4
Pin Configuration and Functions
4.1
Pin Diagrams
4.2
Pin Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Characteristics
5.7
PMBus/SMBus/I2C Timing
5.8
Parametric Measurement Information
5.9
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
ARM Processor
6.3
Memory
6.4
Feature Description
6.4.1
System Module
6.4.1.1
Address Decoder (DEC)
6.4.1.2
Memory Management Controller (MMC)
6.4.1.3
System Management (SYS)
6.4.1.4
Central Interrupt Module (CIM)
6.4.2
Peripherals
6.4.2.1
Digital Power Peripherals
6.4.2.1.1
Front End
6.4.2.1.2
DPWM Module
6.4.2.1.3
DPWM Events
6.4.2.1.4
High Resolution DPWM
6.4.2.1.5
Over Sampling
6.4.2.1.6
DPWM Interrupt Generation
6.4.2.1.7
DPWM Interrupt Scaling/Range
6.4.3
Synchronous Rectifier Dead Time Optimization Peripheral
6.4.4
Automatic Mode Switching
6.4.4.1
Phase Shifted Full Bridge Example
6.4.4.2
LLC Example
6.4.4.3
Mechanism For Automatic Mode Switching
6.4.5
DPWMC, Edge Generation, IntraMux
6.4.6
Filter
6.4.6.1
Loop Multiplexer
6.4.6.2
Fault Multiplexer
6.4.7
Communication Ports
6.4.7.1
SCI (UART) Serial Communication Interface
6.4.7.2
PMBUS/I2C
6.4.7.3
SPI
6.4.8
Timers
6.4.8.1
24-Bit Timer
6.4.8.2
16-Bit PWM Timers
6.4.8.3
Watchdog Timer
6.4.9
General Purpose ADC12
6.4.10
Miscellaneous Analog
6.4.11
Brownout
6.4.12
Global I/O
6.4.13
Temperature Sensor Control
6.4.14
I/O Mux Control
6.4.15
Current Sharing Control
6.4.16
Temperature Reference
6.5
Device Functional Modes
6.5.1
DPWM Modes Of Operation
6.5.1.1
Normal Mode
6.5.1.2
Phase Shifting
6.5.1.3
DPWM Multiple Output Mode
6.5.1.4
DPWM Resonant Mode
6.5.2
Triangular Mode
6.5.3
Leading Edge Mode
6.6
Memory
6.6.1
Register Maps
6.6.1.1
CPU Memory Map and Interrupts
6.6.1.1.1
Memory Map (After Reset Operation)
6.6.1.1.2
Memory Map (Normal Operation)
6.6.1.1.3
Memory Map (System and Peripherals Blocks)
6.6.1.2
Boot ROM
6.6.1.3
Customer Boot Program
6.6.1.4
Flash Management
6.6.1.5
Synchronous Rectifier MOSFET Ramp and IDE Calculation
7
Applications, Implementation, and Layout
7.1
Application Information
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
7.2.2.2
DPWM Initialization for PSFB
7.2.2.2.1
DPWM Synchronization
7.2.2.3
Fixed Signals to Bridge
7.2.2.4
Dynamic Signals to Bridge
7.2.2.5
System Initialization for PCM
7.2.2.5.1
Use of Front Ends and Filters in PSFB
7.2.2.5.2
Peak Current Detection
7.2.2.5.3
Peak Current Mode (PCM)
7.2.3
Application Curves
7.2.4
Power Supply Recommendations
7.2.5
Layout
7.2.5.1
IC Grounding and Layout Guidelines
7.2.5.2
Layout Example
8
器件和文档支持
8.1
器件支持
8.2
文档支持
8.2.1
相关文档
8.3
社区资源
8.4
商标
8.5
静电放电警告
8.6
Glossary
9
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
RGC|64
MPQF125F
散热焊盘机械数据 (封装 | 引脚)
RGC|64
QFND102O
订购信息
zhcser5_oa
2 修订历史记录
日期
修订版本
注释
2015 年 12 月
*
最初发布版本
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