12.1 Device Grounding and Layout Guidelines

• Single ground is recommended: SGND. A multilayer such as 4 layers board is recommended so that one solid SGND is dedicated for return current path, referred to the layout example.
• Apply multiple different capacitors for different frequency range on decoupling circuits. Each capacitor has different ESL, Capacitance and ESR, and they have different frequency response.
• Avoid long traces close to radiation components, and place them into an internal layer, and it is preferred to have grounding shield.
• Analog circuits and digital circuits should have separate return to ground; although with a single plane, still try to avoid mixing analog current and digital current.
• Do not use a ferrite bead or larger than 3-Ω resistor to connect between V33A and V33D.
• Both 3.3VD and 3.3VA should have local decoupling capacitors close to the device power pins, add vias to connect decoupling caps directly to SGND.
• Avoid negative current/negative voltage on all pins, so Schottky clamping diodes may be needed to limit the voltage; avoid more than 3.8 V or less than –0.3 V voltage spikes on all pins; add Schottky diodes on the pins which could have voltage spikes during surge test; be aware that a Schottky has relatively higher leakage current, which can affect the voltage sensing at high temperature.
• If V33 slew rate is less than 2.5 V/ms the RESET pin should have a 2.21-kΩ resistor between the reset pin and V33D and a 2.2-µF capacitor from RESET to ground. For more details please refer to the UCD3138 Family - Practical Design Guideline This capacitor must be located close to the device RESET pin.
• If the XTAL_IN (Pin 61) and XTAL_OUT (Pin 62) are not used for external clock, tie them to 1.8 V (Pin BP18) through a 1-kΩ resistor respectively.
• Configure unused GPIO pins to be inputs or connect them to the ground (DGND or SGND); when an external pull-up resistor is used for GPIO, the pull-up resistor needs to be 1 kΩ or higher.

For detailed practical design guidelines, refer to (UCD3138 Family - Practical Design Guideline).

12.2 Layout Examples

Figure 53. Layout Example for UCD3138128A Top Layer

Figure 54. Layout Example for UCD3138128A Internal Ground Layer