5.8.1.1 Front End

Figure 5-5 shows the block diagram of the front end module. It consists of a differential amplifier, an adjustable gain error amplifier, a high speed flash analog to digital converter (EADC), digital averaging filters and a precision high resolution set point DAC reference. The programmable gain amplifier in concert with the EADC and the adjustable digital gain on the EADC output work together to provide 9 bits of range with 6 bits of resolution on the EADC output. The output of the Front End module is a 9-bit sign extended result with a gain of 1 LSB / mV. Depending on the value of AFE selected, the resolution of this output could be either 1, 2, 4 or 8 LSBs. In addition each EADC has the ability to automatically select the AFE value such that the minimum resolution is maintained that still allows the voltage to fit within the range of the measurement. The EADC control logic receives the sample request from the DPWM module for initiating an EADC conversion. EADC control circuitry captures the EADC-9-bit-code and strobes the digital compensator for processing of the representative error. The set point DAC has 10 bits with an additional 4 bits of dithering resulting in an effective resolution of 14 bits. This DAC can be driven from a variety of sources to facilitate things like soft start, nested loops, and so on. Some additional features include the ability to change the polarity of the error measurement and an absolute value mode which automatically adds the DAC value to the error.

It is possible to operate the controller in a peak current mode control configuration; an EADC is recommended for implementing peak current mode control. In this mode, topologies like a phase shifted full bridge converter can be controlled to maintain transformer flux balance. The internal DAC can be ramped at a synchronously controlled slew rate to achieve a programmable slope compensation. This eliminates the sub-harmonic oscillation as well as improves input voltage feed-forward performance. A0 is a unity gain buffer used to isolate the peak current mode comparator. The offset of this buffer is specified in Section 5.4.

Figure 5-5 Input Stage of EADC Module

Figure 5-6 Front End Module
(Front End 2 Recommended for Peak Current Mode Control)

5.8.1.2 DPWM Module

The DPWM module represents one complete DPWM channel with 2 independent outputs, A and B. Multiple DPWM modules within the UCD3138A system can be configured to support all key power topologies. DPWM modules can be used as independent DPWM outputs, each controlling one power supply output voltage rail. It can also be used as a synchronized DPWM—with user selectable phase shift between the DPWM channels to control power supply outputs with multiphase or interleaved DPWM configurations.

The output of the filter feeds the high resolution DPWM module. The DPWM module produces the pulse width modulated outputs for the power stage switches. The compensator calculates the duty ratio as a 24-bit number in Q23 fixed point format (23 bit integer with 1 sign bit). This represents a value within the range 0.0 to 1.0. This duty ratio value is used to generate the corresponding DPWM output ON time. The resolution of the DPWM ON time is 250 psec.

Each DPWM module can be synchronized to another module or to an external sync signal. An input SYNC signal causes a DPWM ramp timer to reset. The SYNC signal outputs—from each of the four DPWM modules—occur when the ramp timer crosses a programmed threshold. In this way the phase of the DPWM outputs for multiple power stages can be tightly controlled.

The DPWM logic is probably the most complex of the Digital Peripherals. It receives the output of the compensator and converts it into the correct DPWM output for several power supply topologies. It provides for programmable dead times and cycle adjustments for current balancing between phases. It controls the triggering of the EADC. It can synchronize to other DPWMs or to external sources. It can provide synchronization information to other DPWMs or to external recipients. In addition, it interfaces to several fault handling circuits. Some of the control for these fault handling circuits is in the DPWM registers. Fault handling is covered in the Fault Mux section.

Each DPWM module supports the following features:

• Dedicated 14 bit time-base with period and frequency control
• Shadow period register for end of period updates.
• Quad-event control registers (A and B, rising and falling) (Events 1 to 4)
  • Used for on/off DPWM duty ratio updates.
• Phase control relative to other DPWM modules
• Sample trigger placement for output voltage sensing at any point during the DPWM cycle.
• Support for two independent edge placement DPWM outputs (same frequency or period setting)
• Dead-time between DPWM A and B outputs
• High Resolution capabilities – 250 ps
• Pulse cycle adjustment of up to ±8.192 µs (32768 × 250 ps)
• Active high/ active low output polarity selection
• Provides events to trigger both CPU interrupts and start of ADC12 conversions.

5.8.1.3 DPWM Events

Each DPWM can control the following timing events:

1. Sample Trigger Count–This register defines where the error voltage is sampled by the EADC in relationship to the DPWM period. The programmed value set in the register should be one fourth of the value calculated based on the DPWM clock. The clock controlling the circuitry runs at one fourth of the DPWM clock (PCLK = 250 MHz max). When this sample trigger count is equal to the DPWM Counter, it initiates a front end calculation by triggering the EADC, resulting in a CLA calculation, and a DPWM update. Oversampling can be set for 2, 4, or 8 times the sampling rate.
2. Phase Trigger Count – count offset for slaving another DPWM (Multi-Phase/Interleaved operation).
3. Period – low resolution switching period count. (count of PCLK cycles)
4. Event 1 – count offset for rising DPWM A event. (PCLK cycles)
5. Event 2 – DPWM count for falling DPWM A event that sets the duty ratio. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts.
6. Event 3 – DPWM count for rising DPWM B event. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts.
7. Event 4 – DPWM count for falling DPWM B event. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts.
8. Cycle Adjust – Constant offset for Event 2 and Event 4 adjustments.

Basic comparisons between the programmed registers and the DPWM counter can create the desired edge placements in the DPWM. High resolution edge capability is available on Events 2, 3, and 4.

Figure 5-7 is for multi-mode, open loop. Open loop means that the DPWM is controlled entirely by its own registers, not by the filter output. In other words, the power supply control loop is not closed.

The Sample Trigger signals are used to trigger the front end to sample input signals. The Blanking signals are used to blank fault measurements during noisy events, such as FET turn on and turn off.

Events which change with DPWM mode:

• DPWM A Rising Edge = Event 1
• DPWM A Falling Edge = Event 2 + Cycle Adjust A
• DPWM B Rising Edge = Event 3
• DPWM B Falling Edge = Event 4 + Cycle Adjust B
• Phase Trigger = Phase Trigger Register value or Filter Duty

Events always set by their registers, regardless of mode:

• Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
• Begin, Blanking B End

Figure 5-7 Multi Mode Open Loop

5.8.1.4 High Resolution DPWM

Unlike conventional PWM controllers where the frequency of the clock dictates the maximum resolution of PWM edges, the UCD3138A DPWM can generate waveforms with resolutions as small as 250 ps. This is 16× the resolution of the clock driving the DPWM module.

This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz. The high resolution section of DPWM can be enabled or disabled, and the resolution can be defined in several steps between 4 ns to 250 ps. This is done by setting the values of PWM_HR_MULTI_OUT_EN and HIRES_SCALE inside the DPWM Control register 1. See the Power Peripherals programmer’s manual for details.

5.8.1.5 Oversampling

The DPWM module has the capability to trigger an oversampling event by initiating the EADC to sample the error voltage. The default 00 configuration has the DPWM trigger the EADC once based on the sample trigger register value. The over sampling register has the ability to trigger the sampling 2, 4 or 8 times per PWM period. Thus the time the over sample happens is at the divide by 2, 4, or 8 time set in the sampling register. The 01 setting triggers 2X oversampling, the 10 setting triggers 4X over sampling, and the 11 triggers oversampling at 8X.

5.8.1.6 DPWM Interrupt Generation

The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in the period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower interrupt service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12 trigger for sequence synchronization. Table 5-1 outlines the divide ratios that can be programmed.

5.8.1.7 DPWM Interrupt Scaling/Range

5.8.1.8 Synchronous Rectifier Dead Time Optimization Peripheral

The UCD3138A has an advanced dead time control interface where it can accept UCD7138 output signals and optimize SR gate driver signals accordingly. The UCD7138 low-side MOSFET driver is a high-performance driver for secondary-side synchronous rectification (SR) with body diode conduction sensing. The device is suitable for high power high efficiency isolated converter applications where dead-time optimization is desired. The UCD7138 gate driver is a companion device to UCD3138A highly integrated digital controller for isolated power.

Figure 5-8 Synchronous Rectifier Peripheral use with Synchronous Rectifier Driver

DTC0 and DTC1 are received body diode conduction inputs from UCD7138. SR0_DPWM and SR1_DPWM are the DPWM waveforms for the SRs. The red and green edges are moving edges controlled by both the filter output and the DTC interface. In each cycle, right after the falling edge of the SR DPWM waveform, a body diode conduction time detection window is generated. The detection window is defined by both DETECT_BLANK and DETECT_LEN registers. During this detection window, a 4-ns timer capture counts how long the body diode conducts. Then the DPWM turn off edge of the next cycle is adjusted accordingly.

Figure 5-9 Timing Diagram of the DTC Interface

Figure 5-10 shows how the turn off edge is adjusted based on the DTC measurement of the previous cycle. The A_ADJ and B_ADJ registers in DTCMONITOR are signed accumulators; default value is 0.

Figure 5-10 DTC Interface Principle

Based on the DTC measured, in the next cycle:

• A_ADJ = A_ADJ + A_∆
• A_ADJ = A_ADJ + B_∆

In each cycle, the A_ADJ and B_ADJ accumulator values are dynamically adjust the dead time. The ∆ value changes after the measured body diode conduction time. A_ADJ and B_ADJ have been measured and compared to the threshold values in automatic control mode. A_ADJ and B_ADJ can be controlled by firmware while in manual control mode.

Other figures of this peripheral include negative current fault protection, consecutive fault counter, DTC input multiplexor, etc. For details, refer to the programmer's manual.