6.3.1 CPU Memory Map and Interrupts

When the device comes out of power-on-reset, the data memories are mapped to the processor as follows:

6.3.2 Boot ROM

The UCD3138A incorporates a 4k boot ROM. This boot ROM includes support for:

• Program download through the PMBus
• Device initialization
• Examining and modifying registers and memory
• Verifying and executing program FLASH automatically
• Jumping to a customer defined boot program

The Boot ROM is entered automatically on device reset. It initializes the device and then performs checksums on the Program FLASH. If the first 2 kB of program FLASH has a valid checksum, the program jumps to location 0 in the Program FLASH. This permits the use of a customer boot program. If the first checksum fails, it performs a checksum on the complete 32 kB of program flash. If this is valid, it also jumps to location 0 in the program flash. This permits full automated program memory checking, when there is no need for a custom boot program.

If neither checksum is valid, the Boot ROM stays in control, and accepts commands via the PMBus interface

These functions can be used to read and write to all memory locations in the UCD3138. Typically they are used to download a program to Program Flash, and to command its execution

6.3.3 Customer Boot Program

As described above, it is possible to generate a user boot program using 2 kB or more of the program flash. This can support things which the Boot ROM does not support, including:

• Program download via UART – useful especially for applications where the UCD3138A is isolated from the host (for example, PFC)
• Encrypted download – useful for code security in field updates.

6.3.4 Flash Management

The UCD3138A offers a variety of features providing for easy prototyping and easy flash programming. At the same time, high levels of security are possible for production code, even with field updates. Standard firmware will be provided for storing multiple copies of system parameters in data flash. This is minimizes the risk of losing information if programming is interrupted.

6.4.1 Address Decoder (DEC)

The Address Decoder generates the memory selects for the FLASH, ROM and RAM arrays. The memory map addresses are selectable through configurable register settings. These memory selects can be configured from 1 kB to 16 MB. Power on reset uses the default addresses in the memory map for ROM execution, which is then configured by the ROM code to the application setup. During access to the DEC registers, a wait state is asserted to the CPU. DEC registers are only writable in the ARM privilege mode for user mode protection.

6.4.2 Memory Management Controller (MMC)

The MMC manages the interface to the peripherals by controlling the interface bus for extending the read and write accesses to each peripheral. The unit generates eight peripheral select lines with 1 kB of address space decoding.

6.4.3 System Management (SYS)

The SYS unit contains the software access protection by configuring user privilege levels to memory or peripherals modules. It contains the ability to generate fault or reset conditions on decoding of illegal address or access conditions. A clock control setup for the processor clock (MCLK) speed, is also available.

6.4.4 Central Interrupt Module (CIM)

The CIM accepts 32 interrupt requests for meeting firmware timing requirements. The ARM processor supports two interrupt levels: FIQ and IRQ. FIQ is the highest priority interrupt. The CIM provides hardware expansion of interrupts by use of FIQ/IRQ vector registers for providing the offset index in a vector table. This numerical index value indicates the highest precedence channel with a pending interrupt and is used to locate the interrupt vector address from the interrupt vector table. Interrupt channel 0 has the lowest precedence and interrupt channel 31 has the highest precedence. To remove the interrupt request, the firmware should clear the request as the first action in the interrupt service routine. The request channels are maskable, allowing individual channels to be selectively disabled or enabled.

6.5.1 Normal Mode

In Normal mode, the Filter output determines the pulse width on DPWM A. DPWM B fits into the rest of the switching period, with a dead time separating it from the DPWM A on-time. It is useful for buck topologies. The drawing of the Normal Mode waveforms is shown in Figure 6-1.

Cycle adjust A can be used to adjust pulse widths on individual phases of a multi-phase system. This can be used for functions like current balancing. The Adaptive Sample Triggers can be used to sample in the middle of the on-time (for an average output), or at the end of the on-time (to minimize phase delay) The Adaptive Sample Register provides an offset from the center of the on-time. This can compensate for external delays, such as MOSFET and gate driver turn on times.

Blanking A-Begin and Blanking A-End can be used to blank out noise from the MOSFET turn on at the beginning of the period (DPWMA rising edge). Blanking B could be used at the turn off time of DPWMB. The other edges are dynamic, so blanking is more difficult.

Cycle Adjust B has no effect in Normal Mode.

Events which change with DPWM mode:

• DPWM A Rising Edge = Event 1
• DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A
• Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or
• Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
• DPWM B Rising Edge = Event 1 + Filter Duty + Cycle Adjust A + (Event 3 – Event 2)
• DPWM B Falling Edge = Event 4 + DTC Adjustment
• Phase Trigger = Phase Trigger Register value or Filter Duty

Events always set by their registers, regardless of mode:

• Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
• Begin, Blanking B End

Figure 6-1 Normal Mode Closed Loop

6.5.2 DPWM Multiple Output Mode

Multi mode is used for systems where each phase has only one driver signal. It enables each DPWM peripheral to drive two phases with the same pulse width, but with a time offset between the phases, and with different cycle adjusts for each phase.

The diagram for Multi-Mode is shown in Figure 6-2.

Event 2 and Event 4 are not relevant in Multi mode.

DPWMB can cross over the period boundary safely, and still have the proper pulse width, so full 100% pulse width operation is possible. DPWMA cannot cross over the period boundary.

Since the rising edge on DPWM B is also fixed, Blanking B-Begin and Blanking B-End can be used for blanking this rising edge.

Cycle Adjust B is usable on DPWM B.

Events which change with DPWM mode:

• DPWM A Rising Edge = Event 1
• DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A + DTC Adjustment
• Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or
• Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
• DPWM B Rising Edge = Event 3
• DPWM B Falling Edge = Event 3 + Filter Duty + Cycle Adjust B + DTC Adjustment
• Phase Trigger = Phase Trigger Register value or Filter Duty

Events always set by their registers, regardless of mode:

• Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
• Begin, Blanking B End

Figure 6-2 Multi Mode Closed Loop

6.5.3 DPWM Resonant Mode

This mode provides a symmetrical waveform where DPWMA and DPWMB have the same pulse width. As the switching frequency changes, the dead times between the pulses remain the same.

The equations for this mode are designed for a smooth transition from PWM mode to resonant mode, as described in Section 6.7.2. The diagram of this mode is shown in Figure 6-3.

The Filter has two outputs, Filter Duty and Filter Period. In this case, the Filter is configured so that the Filter Period is twice the Filter Duty. So if there were no dead times, each DPWM pin would be on for half of the period. For dead time handling, the average of the two dead times is subtracted from the Filter Duty for both DPWM pins. Therefore, both pins will have the same on-time, and the dead times will be fixed regardless of the period. The only edge which is fixed relative to the start of the period is the rising edge of DPWM A. This is the only edge for which the blanking signals can be used easily.

Events which change with DPWM mode:

• Dead Time 1 = Event 3 - Event 2
• Dead Time 2 = Event 1 + Period Register - Event 4
• Average Dead Time = (Dead Time 1 + Dead Time 2)/2
• DPWM A Rising Edge = Event 1
• DPWM A Falling Edge = Event 1 + Filter Duty - Average Dead Time + DTC Adjustment
• Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or
• Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
• DPWM B Rising Edge = Event 1 + Filter Duty - Average Dead Time + (Event 3 - Event 2)
• DPWM B Falling Edge = Filter Period - (Period Register - Event 4) + DTC Adjustment
• Phase Trigger = Phase Trigger Register value or Filter Duty

Events always set by their registers, regardless of mode:

• Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
• Begin, Blanking B End

Figure 6-3 Resonant Symmetrical Closed Loop

6.5.4 Triangular Mode

Triangular mode provides a stable phase shift in interleaved PFC and similar topologies. In this case, the PWM pulse is centered in the middle of the period, rather than starting at one end or the other. In Triangular Mode, only DPWM-B is available. The diagram for Triangular Mode is shown in Figure 6-4.

All edges are dynamic in triangular mode, so fixed blanking is not that useful. The adaptive sample trigger is not needed. It is very easy to put a fixed sample trigger exactly in the center of the FET on-time, because the center of the on-time does not move in this mode.

Events which change with DPWM mode:

• DPWM A Rising Edge = None
• DPWM A Falling Edge = None
• Adaptive Sample Trigger = None
• DPWM B Rising Edge = Period / 2 - Filter Duty / 2 + Cycle Adjust A
• DPWM B Falling Edge = Period / 2 + Filter Duty / 2 + Cycle Adjust B
• Phase Trigger = Phase Trigger Register value or Filter Duty

Events always set by their registers, regardless of mode:

• Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
• Begin, Blanking B End

Figure 6-4 Triangular Mode Closed Loop

6.5.5 Leading Edge Mode

Leading edge mode is very similar to Normal mode, reversed in time. The DPWM A falling edge is fixed, and the rising edge moves to the left, or backwards in time, as the filter output increases. The DPWM B falling edge stays ahead of the DPWMA rising edge by a fixed dead time. The diagram of the Leading Edge Mode is shown in Figure 6-5.

As in the Normal mode, the two edges in the middle of the period are dynamic, so the fixed blanking intervals are mainly useful for the edges at the beginning and end of the period.

Events which change with DPWM mode:

• DPWM A Rising Edge = Event 1
• DPWM A Falling Edge = = Event 1 - Filter Duty + Cycle Adjust A
• Adaptive Sample Trigger A = Event 1 - Filter Duty + Adaptive Sample Register or
• Adaptive Sample Trigger B = Event 1 - Filter Duty / 2 + Adaptive Sample Register
• DPWM B Rising Edge = Event 4
• DPWM B Falling Edge = Event 1 - Filter Duty + Cycle Adjust A - ( Event 2 – Event 3 )
• Phase Trigger = Phase Trigger Register value or Filter Duty

Events always set by their registers, regardless of mode:

• Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
• Begin, Blanking B End

Figure 6-5 Leading Edge Closed Loop

6.7.1 Phase Shifted Full Bridge Example

Phase shifted full bridge topologies are shown in Figure 6-6 and Figure 6-7.

Figure 6-6 Phase Shifted Full Bridge

Figure 6-7 Secondary-Referenced Phase-Shifted Full Bridge Control
With Synchronous Rectification

6.7.2 LLC Example

In LLC, three modes are used. At the highest frequency, a pulse width modulated mode (Multi Mode) is used. As the frequency decreases, resonant mode is used. As the frequency gets still lower, the synchronous MOSFET drive changes so that the on-time is fixed and does not increase. In addition, the LLC control supports cycle-by-cycle current limiting. This protection function operates by a comparator monitoring the maximum current during the DPWMA conduction time. Any time this current exceeds the programmable comparator reference the pulse is immediately terminated. Due to classic instability issues associated with half-bridge topologies it is also possible to force DPWMB to match the truncated pulse width of DPWMA. Here are the waveforms for the LLC:

Figure 6-8 Secondary-Referenced Half-Bridge Resonant LLC Control
With Synchronous Rectification

6.7.3 Mechanism for Automatic Mode Switching

The UCD3138A allows the customer to enable up to two distinct levels of automatic mode switching. These different modes are used to enhance light load operation, short circuit operation and soft start. Many of the configuration parameters for the DPWM are in DPWM Control Register 1. For automatic mode switching, some of these parameters are duplicated in the Auto Config Mid and Auto Config High registers.

If automatic mode switching is enabled, the filter duty signal is used to select which of these three registers is used. There are 4 registers which are used to select the points at which the mode switching takes place. They are used as shown in Figure 6-9.

Figure 6-9 Automatic Mode Switching

As shown, the registers are used in pairs for hysteresis. The transition from Control Register 1 to Auto Config Mid only takes place when the Filter Duty goes above the Low Upper threshold. It does not go back to Auto Config Mid until the Low Lower Threshold is passed. This prevents oscillation between modes if the filter duty is close to a mode switching point.

6.9.1 Loop Multiplexer

The Loop Mux controls interconnections between the filters, front ends, and DPWMs. Any filter, front end, and DPWM can be combined with each other in many configurations.

It also controls the following connections:

• DPWM to Front End
• Front End DAC control from Filters or Constant Current/Constant Power Module
• Filter Special Coefficients and Feed Forward
• DPWM synchronization
• Filter to DPWM

The following control modules are configured in the Loop Mux:

• Constant Power/Constant Current
• Cycle Adjustment (Current and flux balancing)
• Global Period
• Light Load (Burst Mode)
• Analog Peak Current Mode

6.9.2 Fault Multiplexer

In order to allow a flexible way of mapping several fault triggering sources to all the DPWMs channels, the UCD3138A provides an extensive array of multiplexers that are united under the name Fault Mux module.

The Fault Mux Module supports flexible mapping between fault sources and fault response mechanism inside each DPWM module.

• Many fault sources can be mapped to a single fault response mechanism. For instance an analog comparator in charge of over voltage protection, a digital comparator in charge of over current protection and an external digital fault pin can be all mapped to a fault-A signal connected to a single FAULT MODULE and shut down DPWM1-A.
• A single fault source can be mapped to many fault response mechanisms inside many DPWM modules. For instance an analog comparator in charge of over current protection can be mapped to DPWM-0 through DPWM-3 by way of several fault modules.

The Fault Mux Module provides a multitude of fault protection functions within the UCD3138A high-speed loop (front end control, filter, DPWM and loop Mux modules). The Fault Mux Module allows highly configurable fault generation based on digital comparators, high-speed analog comparators and external fault pins. Each of the fault inputs to the DPWM modules can be configured to one or any combination of the fault events provided in the Fault Mux Module.

Each one of the DPWM engines has four fault modules. The modules are called CBC fault module, AB fault module, A fault module and B fault module.

The internal circuitry in all the four fault modules is identical, and the difference between the modules is limited to the output it affects under a fault condition.

Figure 6-15 Fault Module

All fault modules are capable of detecting faults only once per DPWM switching cycle. Each one of the fault modules have a separate max_count and the fault flag will be set only if sequential faults count exceeds max_count.

Once the fault flag is set DPWMs need to be disabled by DPWM_EN going low in order to clear the fault flags. Note, all four Fault Modules share the same DPWM_EN control, all fault flags (output of Fault Modules) is cleared simultaneously.

All four Fault Modules share the same global FAULT_EN as well. Therefore, a specific Fault Module cannot be enabled/ disabled separately.

Figure 6-16 Cycle by Cycle Block

In contrast to the fault modules, only one cycle by cycle block is available in each DPWM module.

The cycle by cycle block can work in conjunction with CBC Fault Module and enables DPWM reaction to signals arriving from analog peak current mode (PCM) module.

The fault Mux module supports the following basic functions:

• 4 digital comparators with programmable thresholds and fault generation
• Configuration for 7 high-speed analog comparators with programmable thresholds and fault generation
• External GPIO detection control with programmable fault generation
• Configurable DPWM fault generation for DPWM current limit fault, DPWM overvoltage detection fault, DPWM A external fault, DPWM B external fault and DPWM IDE flag
• Clock failure detection for high and low frequency oscillator blocks
• Discontinuous conduction mode detection

Figure 6-17 Fault Mux Block Diagram

6.10.1 SCI (UART) Serial Communication Interface

A maximum of two independent Serial Communication Interface (SCI) or Universal Asynchronous Receiver/Transmitter pre-scaler (UART) interfaces are included within the device for asynchronous start-stop serial data communication (see the pin out sections for details) Each interface has a 24 bit for supporting programmable baud rates and has programmable data word and stop bit options. Half or full duplex operation is configurable through register bits. A loop back feature can also be setup for firmware verification. Both SCI-TX and SCI-RX pin sets can be used as GPIO pins when the peripheral is not being used. Both the UART ports support Hardware auto baud correction improving robustness in communication even at higher baud rates.

6.10.2 PMBUS

The PMBus Interface supports independent master and slave modes controlled directly by firmware through a processor bus interface. Individual control and status registers enable firmware to send or receive I2C, SMBus or PMBus messages in any of the accepted protocols, in accordance with the I²C Specification, SMBus Specification (Version 2.0) and the PMBUS Power System Management Protocol Specification (PMBus 1.3).

The PMBus interface is controlled through a processor bus interface, utilizing a 32-bit data bus and 6-bit address bus. The PMBus interface is connected to the expansion bus, which features 4 byte write enables, a peripheral select dedicated for the PMBus interface, separated 32-bit data buses for reading and writing of data and active-low write and output enable control signals. In addition, the PMBus Interface connects directly to the I²C/SMBus/PMBus Clock, Data, Alert, and Control signals.

Example: PMBus Address Decode via ADC12 Reading

The user can allocate 2 pins of the 12-bit ADC input channels, AD_00 and AD_01, for PMBus address decoding. At power-up the device applies I_BIAS to each address detect pin and the voltage on that pin is captured by the internal 12-bit ADC.

Where bin(V_AD0x) is the address bin for one of 12 address as shown in Figure 6-18.

Figure 6-18 PMBus Address Detection Method

6.10.3 General Purpose ADC12

The ADC12 is a 12 bit, high speed analog to digital converter, equipped with the following options:

• Typical conversion speed of 267 ksps
• Conversions can consist from 1 to 16 ADC channel conversions in any desired sequence
• Post conversion averaging capability, ranging from 4X, 8X, 16X or 32X samples
• Configurable triggering for ADC conversions from the following sources: firmware, DPWM rising edge, ADC_EXT_TRIG pin or Analog Comparator results
• Interrupt capability to embedded processor at completion of ADC conversion
• Six digital comparators on the first 6 channels of the conversion sequence using either raw ADC data or averaged ADC data
• Two 10 µA current sources for excitation of PMBus addressing resistors
• Dual sample and hold for accurate power measurement
• Internal temperature sensor for temperature protection and monitoring

The control module ADC12 Contol Block Diagram contains the control and conversion logic for auto-sequencing a series of conversions. The sequencing is fully configurable for any combination of 16 possible ADC channels through an analog multiplexer embedded in the ADC12 block. Once converted, the selected channel value is stored in the result register associated with the sequence number. Input channels can be sampled in any desired order or programmed to repeat conversions on the same channel multiple times during a conversion sequence. Selected channel conversions are also stored in the result registers in order of conversion, where the result 0 register is the first conversion of a 16-channel sequence and result 15 register is the last conversion of a 16-channel sequence. The number of channels converted in a sequence can vary from 1 to 16.

Unlike EADC0 through EADC2, which are primarily designed for closing high speed compensation loops, the ADC12 is not usually used for loop compensation purposes. The EADC converters have a substantially faster conversion rate, thus making them more attractive for closed loop control. The ADC12 features make it best suited for monitoring and detection of currents, voltages, temperatures and faults. Please see the Typical Characteristics plots for the temperature variation associated with this function.

Figure 6-19 ADC12 Control Block Diagram

6.10.4 Timers

External to the Digital Power Peripherals there are 3 different types of timers in UCD3138A. They are the 24-bit timer, 16-bit timer and the Watchdog timer