米6体育平台手机版

ZHCSCX7B June 2014 – February 2017 UCD3138128 , UCD3138A64

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PFC|80
- MTQF009B

散热焊盘机械数据 (封装 | 引脚)

订购信息

9 Detailed Description

9.1 Overview

9.1.1 ARM Processor

The ARM7TDMI-S processor is a synthesizable member of the ARM family of general purpose 32-bit microprocessors. The ARM architecture is based on RISC (Reduced Instruction Set Computer) principles where two instruction sets are available. The 32-bit ARM instruction set and the 16-bit Thumb instruction set. The Thumb instructions allow for higher code density equivalent to a 16-bit microprocessor, with the performance of the 32-bit microprocessor.

The three-staged pipelined ARM processor has fetch, decode and execute stage architecture. Major blocks in the ARM processor include a 32-bit ALU, 32 x 8 multiplier, and a barrel shifter.

9.1.2 Memory

The UCD3138x (ARM7TDMI-S) is a Von-Neumann architecture, where a single bus provides access to all of the memory modules. All of the memory module addresses are sequentially aligned along the same address range. This applies to program flash, data flash, ROM and all other peripherals.

Within the UCD3138 family architecture, there is a 1024x32-bit Boot ROM that contains the initial firmware startup routines for PMBUS communication and non-volatile (FLASH) memory download. This boot ROM is executed after power-up-reset checks if there is a valid FLASH program written. If a valid program is present, the ROM code branches to the main FLASH-program execution. If there is no valid program, the device waits for a program download through the PMBus.

The UCD3138 family also supports customization of the boot program by allowing an alternative boot routine to be executed from program FLASH. This feature enables assignment of a unique address to each device; therefore, enabling firmware reprogramming even when several devices are connected on the same communication bus.

There are three separate flash memory areas present inside the device. There are 2-32 kB program flash blocks and 1-2 kB data flash area. The 32 kB program areas are organized as 8 k x 32 bit memory blocks and are intended to be for the firmware programs. The blocks are configured with page erase capability for erasing blocks as small as 1 kB per page, or with a mass erase for erasing the entire 32 kB array. The flash endurance is specified at 1000 erase/write cycles and the data retention is good for 100 years. The 2 kB data flash array is organized as a 512 x 32 bit memory (32 byte page size). The data flash is intended for firmware data value storage and data logging. Thus, the Data flash is specified as a high endurance memory of 20 k cycles with embedded error correction code (ECC).

For run time data storage and scratchpad memory, a 8 kB RAM is available. The RAM is organized as a 2 k x 32 bit array.

The availability of 64 kB or 128 kB of program Flash memory in 2-32 kB or 4-32 kB banks, respectively enables the designers to implement multiple images of firmware (e.g. one main image + one back-up image) in the device and the flexibility to execute from either of the banks using appropriate algorithms. It also creates the unique opportunity for the processor to load a new program and subsequently execute that program without interrupting power delivery. This feature allows the end user to add new features to the power supply while eliminating any down-time required to load the new program.

The UCD3138128 adds two additional 32 kB program flash blocks. On the UCD3138128, the boot ROM supports a dual image configuration where each image contains 64 kB. If the first 64kB has an invalid program, the boot ROM will check for a valid program in the second 64kB and jump there. The boot ROM also supports a configuration with a single program occupying the entire 128 kB.

For the UCD3138128, on the fly updates are supported through boot ROM while UCD3138A64 on the fly updates are supported through boot flash. Detailed procedures can be found in SLUUB54

9.2 Functional Block Diagram

UCD3138128 UCD3138A64 fbd_CycloneA64_SLUSBZ8.gif

9.3 Feature Description

9.3.1 System Module

The System Module contains the interface logic and configuration registers to control and configure all the memory, peripherals and interrupt mechanisms. The blocks inside the system module are the address decoder, memory management controller, system management unit, central interrupt unit, and clock control unit.

9.3.1.1 Address Decoder (DEC)

The Address Decoder generates the memory selects for the FLASH, ROM and RAM arrays. The memory map addresses are selectable through configurable register settings. These memory selects can be configured from 1 kB to 16 MB. Power on reset uses the default addresses in the memory map for ROM execution, which is then configured by the ROM code to the application setup. During access to the DEC registers, a wait state is asserted to the CPU. DEC registers are only writable in the ARM privilege mode for user mode protection.

9.3.1.2 Memory Management Controller (MMC)

The MMC manages the interface to the peripherals by controlling the interface bus for extending the read and write accesses to each peripheral. The unit generates eight peripheral select lines with 1 kB of address space decoding.

9.3.1.3 System Management (SYS)

The SYS unit contains the software access protection by configuring user privilege levels to memory or peripherals modules. It contains the ability to generate fault or reset conditions on decoding of illegal address or access conditions. A clock control setup for the processor clock (MCLK) speed, is also available.

9.3.1.4 Central Interrupt Module (CIM)

The CIM accepts 32 interrupt requests for meeting firmware timing requirements. The ARM processor supports two interrupt levels: FIQ and IRQ. FIQ is the highest priority interrupt. The CIM provides hardware expansion of interrupts by use of FIQ/IRQ vector registers for providing the offset index in a vector table. This numerical index value indicates the highest precedence channel with a pending interrupt and is used to locate the interrupt vector address from the interrupt vector table. Interrupt channel 0 has the lowest precedence and interrupt channel 31 has the highest precedence. To remove the interrupt request, the firmware should clear the request as the first action in the interrupt service routine. The request channels are maskable, allowing individual channels to be selectively disabled or enabled.

Table 1. Interrupt Priority Table

NAME	MODULE COMPONENT OR REGISTER	DESCRIPTION	PRIORITY
BRN_OUT_INT	Brownout	Brownout interrupt	0 (Lowest)
EXT_INT	External Interrupts	Interrupt on external input pin	1
WDRST_INT	Watchdog Control	Interrupt from watchdog exceeded (reset)	2
WDWAKE_INT	Watchdog Control	Wake-up interrupt when watchdog equals half of set watch time	3
SCI_ERR_INT	UART or SCI Control	UART or SCI error Interrupt. Frame, parity or overrun	4
SCI_RX_0_INT	UART or SCI Control	UART0 RX buffer has a byte	5
SCI_TX_0_INT	UART or SCI Control	UART0 TX buffer empty	6
SCI_RX_1_INT	UART or SCI Control	UART1 RX buffer has a byte	7
SCI_TX_1_INT	UART or SCI Control	UART1 TX buffer empty	8
PMBUS_INT		PMBus related interrupt	9
DIG_COMP_SPI_I2C_INT	12-bit ADC Control, SPI, I²C	Digital comparator, SPI and I²C interrupt	10
FE0_INT	Front End 0	“Prebias complete”, “Ramp Delay Complete”, “Ramp Complete”, “Load Step Detected”, “Over-Voltage Detected”, “EADC saturated”	11
FE1_INT	Front End 1	“Prebias complete”, “Ramp Delay Complete”, “Ramp Complete”, “Load Step Detected”, “Over-Voltage Detected”, “EADC saturated”	12
FE2_INT	Front End 2	“Prebias complete”, “Ramp Delay Complete”, “Ramp Complete”, “Load Step Detected”, “Over-Voltage Detected”, “EADC saturated”	13
PWM3_INT	16-bit Timer PWM 3	16-bit Timer PWM3 counter overflow or compare interrupt	14
PWM2_INT	16-bit Timer PWM 2	16-bit Timer PWM2 counter Overflow or compare interrupt	15
PWM1_INT	16-bit Timer PWM 1	16-bit Timer PWM1 counter overflow or compare interrupt	16
PWM0_INT	16-bit timer PWM 0	16-bit Timer PWM0 counter overflow or compare interrupt	17
OVF24_INT	24-bit Timer Control	24-bit Timer counter overflow interrupt	18
CAPTURE_1_INT	24-bit Timer Control	24-bit Timer capture 1 interrupt	19
Reserved for future use			20
CAPTURE_0_INT	24-bit Timer Control	24-bit Timer capture 0 interrupt	21
COMP_0_INT	24-bit Timer Control	24-bit Timer compare 0 interrupt	22
CPCC_RTC_INT	Constant Power Constant Current or Real Time Clock Output	Mode switched in CPCC module Flag needs to be read for details. RTC timer output generates an interrupt.	23
ADC_CONV_INT	12-bit ADC Control	ADC end of conversion interrupt	24
FAULT_INT	Fault Mux Interrupt	Analog comparator interrupts, Over-Voltage detection, Under-Voltage detection, LLM load step detection	25
DPWM3	DPWM3	Same as DPWM1	26
DPWM2	DPWM2	Same as DPWM1	27
DPWM1	DPWM1	1) Every (1-256) switching cycles 2) Fault Detection 3) Mode switching	28
DPWM0	DPWM0	Same as DPWM1	29
EXT_FAULT_INT	External Faults	Fault pin interrupt	30
SYS_SSI_INT	System Software	System software interrupt	31 (highest)

9.3.2 Peripherals

9.3.2.1 Digital Power Peripherals

At the core of the UCD3138x controller are 3 Digital Power Peripherals (DPP). Each DPP can be configured to drive from one to eight DPWM outputs. Each DPP consists of:

Differential input error ADC (EADC) with sophisticated controls
Hardware accelerated digital 2-pole/2-zero PID based filter
Digital PWM module with support for a variety of topologies

These can be connected in many different combinations, with multiple filters and DPWMs. They are capable of supporting functions like input voltage feed forward, current mode control, and constant current/constant power, etc.. The simplest configuration is shown in the following figure:

UCD3138128 UCD3138A64 fusion_dig_pwr_lusap2.gif

9.3.2.1.1 Front End

Figure 9 shows the block diagram of the front end module. It consists of a differential amplifier, an adjustable gain error amplifier, a high speed flash analog to digital converter (EADC), digital averaging filters and a precision high resolution set point DAC reference. The programmable gain amplifier in concert with the EADC and the adjustable digital gain on the EADC output work together to provide 9 bits of range with 6 bits of resolution on the EADC output. The output of the Front End module is a 9 bit sign extended result with a gain of 1 LSB / mV. Depending on the value of AFE selected, the resolution of this output could be either 1, 2, 4 or 8 LSBs. In addition Front End 0 has the ability to automatically select the AFE value such that the minimum resolution is maintained that still allows the voltage to fit within the range of the measurement. The EADC control logic receives the sample request from the DPWM module for initiating an EADC conversion. EADC control circuitry captures the EADC-9-bit-code and strobes the filter for processing of the representative error. The set point DAC has 10 bits with an additional 4 bits of dithering resulting in an effective resolution of 14 bits. This DAC can be driven from a variety of sources to facilitate things like soft start, nested loops, etc. Some additional features include the ability to change the polarity of the error measurement and an absolute value mode which automatically adds the DAC value to the error.

It is possible to operate the controller in a peak current mode control configuration. In this mode topologies like the phase shifted full bridge converter can be controlled to maintain transformer flux balance. The internal DAC can be ramped at a synchronously controlled slew rate to achieve a programmable slope compensation. This eliminates the sub-harmonic oscillation as well as improves input voltage feed-forward performance. A0 is a unity gain buffer used to isolate the peak current mode comparator. The offset of this buffer is specified in the Electrical Characteristics table.

UCD3138128 UCD3138A64 REA_IOFFSET_lusap2.gif

Figure 9. Input Stage Of EADC Module

UCD3138128 UCD3138A64 front_end_BD_SLUSBZ8.gif

Figure 10. Front End Module

9.3.2.1.2 DPWM Module

The DPWM module represents one complete DPWM channel with 2 independent outputs, A and B. Multiple DPWM modules within the UCD3138x system can be configured to support all key power topologies. DPWM modules can be used as independent DPWM outputs, each controlling one power supply output voltage rail. It can also be used as a synchronized DPWM—with user selectable phase shift between the DPWM channels to control power supply outputs with multiphase or interleaved DPWM configurations.

The output of the filter feeds the high resolution DPWM module. The DPWM module produces the pulse width modulated outputs for the power stage switches. The filter calculates the necessary duty ratio as a 24-bit number in Q23 fixed point format (23 bit integer with 1 sign bit). This represents a value within the range 0.0 to 1.0. This duty ratio value is used to generate the corresponding DPWM output ON time. The resolution of the DPWM ON time is 250 psec.

Each DPWM module can be synchronized to another module or to an external synchronization signal. An input SYNC signal causes a DPWM ramp timer to reset. The SYNC signal outputs—from each of the four DPWM modules—occur when the ramp timer crosses a programmed threshold. This allows the phase of the DPWM outputs for multiple power stages to be tightly controlled.

The DPWM logic takes the output of the filter and converts it into the correct DPWM output for several power supply topologies. It provides for programmable dead times and cycle adjustments for current balancing between phases. It controls the triggering of the EADC. It can synchronize to other DPWMs or to external sources. It can provide synchronization information to other DPWMs or to external recipients. In addition, it interfaces to several fault handling circuits. Some of the control for these fault handling circuits is in the DPWM registers. Fault handling is covered in the Fault Mux section.

Each DPWM module supports the following features:

Dedicated 14 bit time-base with period and frequency control
Shadow period register for end of period updates.
Quad-event control registers (A and B, rising and falling) (Events 1-4)
- Used for on/off DPWM duty ratio updates.
Phase control relative to other DPWM modules
Sample trigger placement for output voltage sensing at any point during the DPWM cycle.
Support for 2 independent edge placement DPWM outputs (same frequency or period setting)
Dead-time between DPWM A and B outputs
High Resolution PWM capability – 250 ps
Pulse cycle adjustment of up to ±8.192 µs ( 32768 × 250 ps)
Active high/ active low output polarity selection
Provides events to trigger both CPU interrupts and start of ADC12 conversions.

9.3.2.1.3 DPWM Events

Each DPWM can control the following timing events:

Sample Trigger Count–This register defines where the error voltage is sampled by the EADC in relationship to the DPWM period. The programmed value set in the register should be one fourth of the value calculated based on the DPWM clock. As the DCLK (DCLK = 62.5 MHz max) controlling the circuitry runs at one fourth of the DPWM clock (PCLK = 250MHz max). When this sample trigger count is equal to the DPWM Counter, it initiates a front end calculation by triggering the EADC, resulting in a CLA calculation, and a DPWM update. Over-sampling can be set for 2, 4 or 8 times the sampling rate.
Phase Trigger Count–count offset for slaving another DPWM (Multi-Phase/Interleaved operation).
Period–low resolution switching period count. (count of PCLK cycles)
Event 1–count offset for rising DPWM A event. (PCLK cycles)
Event 2–DPWM count for falling DPWM A event that sets the duty ratio. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts.
Event 3–DPWM count for rising DPWM B event. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts.
Event 4–DPWM count for falling DPWM B event. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts.
Cycle Adjust–Constant offset for Event 2 and Event 4 adjustments.

Basic comparisons between the programmed registers and the DPWM counter can create the desired edge placements in the DPWM. High resolution edge capability is available on Events 2, 3 and 4.

UCD3138128 UCD3138A64 mulit2_opn_loop_lusap2.gif

The drawing above is for multi-mode, open loop. Open loop means that the DPWM is controlled entirely by its own registers, not by the filter output. In other words, the power supply control loop is not closed.

The Sample Trigger signals are used to trigger the Front End to sample input signals. The Blanking signals are used to blank fault measurements during noisy events, such as FET turn on and turn off. Additional DPWM modes are described below.

9.3.2.1.4 High Resolution DPWM

Unlike conventional PWM controllers where the frequency of the clock dictates the maximum resolution of PWM edges, the UCD3138x DPWM can generate waveforms with resolutions as small as 250 ps. This is 16 times the resolution of the clock driving the DPWM module.

This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz each.

9.3.2.1.5 Over Sampling

The DPWM module has the capability to trigger an over sampling event by initiating the EADC to sample the error voltage. The default “00” configuration has the DPWM trigger the EADC once based on the sample trigger register value. The over sampling register has the ability to trigger the sampling 2, 4 or 8 times per PWM period. Thus the time the over sample happens is at the divide by 2, 4, or 8 time set in the sampling register. The “01” setting triggers 2X over sampling, the “10” setting triggers 4X over sampling, and the “11” triggers over sampling at 8X.

9.3.2.1.6 DPWM Interrupt Generation

The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in the period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower interrupt service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12 trigger for sequence synchronization. Table 2 outlines the divide ratios that can be programmed.

9.3.2.1.7 DPWM Interrupt Scaling/Range

Table 2. DPWM Interrupt Divide Ratio

INTERRUPT DIVIDE SETTING	INTERRUPT DIVIDE COUNT	INTERRUPT DIVIDE COUNT (HEX)	SWITCHING PERIOD FRAMES (assume 1MHz loop)	NUMBER OF 32 MHZ PROCESSOR CYCLES
1	0	00	1	32
2	1	01	2	64
3	3	03	4	128
4	7	07	8	256
5	15	0F	16	512
6	31	1F	32	1024
7	47	2F	48	1536
8	63	3F	64	2048
9	79	4F	80	2560
10	95	5F	96	3072
11	127	7F	128	4096
12	159	9F	160	5120
13	191	BF	192	6144
14	223	DF	224	7168
15	255	FF	256	8192

9.3.3 Automatic Mode Switching

Automatic Mode switching enables the DPWM module to switch between modes automatically, with no firmware intervention. This is useful to increase efficiency and power range. The following paragraphs describe phase-shifted full bridge and LLC examples.

9.3.3.1 Phase Shifted Full Bridge Example

In phase shifted full bridge topologies, efficiency can be increased by using pulse width modulation, rather than phase shift, at light load. This is shown below:

UCD3138128 UCD3138A64 full2_bridge_lusap2.gif

Figure 11. Phase-Shifted Full Bridge Waveforms

UCD3138128 UCD3138A64 PSFB_blk_dia_lusap2.gif

Figure 12. Secondary-Referenced Phase-Shifted Full Bridge Control With Synchronous Rectification

9.3.3.2 LLC Example

In LLC, three modes are used. At the highest frequency, a pulse width modulated mode (Multi Mode) is used. As the frequency decreases, resonant mode is used. As the frequency gets still lower, the synchronous MOSFET drive changes so that the on-time is fixed and does not increase. In addition, the LLC control supports cycle-by-cycle current limiting. This protection function operates by a comparator monitoring the maximum current during the DPWMA conduction time. Any time this current exceeds the programmable comparator reference the pulse is immediately terminated. Due to classic instability issues associated with half-bridge topologies it is also possible to force DPWMB to match the truncated pulse width of DPWMA. Here are the waveforms for the LLC:

UCD3138128 UCD3138A64 LLC_waveforms_lusap2.gif

Figure 13. LLC Waveforms

UCD3138128 UCD3138A64 LLC_block_dia_lusap2.gif

Figure 14. Secondary-Referenced Half-Bridge Resonant LLC Control With Synchronous Rectification

9.3.3.3 Mechanism For Automatic Mode Switching

The UCD3138x allows the customer to enable up to two distinct levels of automatic mode switching. These different modes are used to enhance light load operation, short circuit operation and soft start. Many of the configuration parameters for the DPWM are in DPWM Control Register 1. For automatic mode switching, some of these parameters are duplicated in the Auto Config Mid and Auto Config High registers.

If automatic mode switching is enabled, the filter duty signal is used to select which of these three registers is used. There are 4 registers which are used to select the points at which the mode switching takes place. They are used as shown below.

UCD3138128 UCD3138A64 auto_swt_lusap2.gif

Figure 15. Automatic Mode Switching

As shown, the registers are used in pairs for hysteresis. The transition from Control Register 1 to Auto Config Mid only takes place when the Filter Duty goes above the Low Upper threshold. It does not go back to Auto Config Mid until the Low Lower Threshold is passed. This prevents oscillation between modes if the filter duty is close to a mode switching point.

9.3.4 DPWMC, Edge Generation, Intramux

The UCD3138x has hardware for generating complex waveforms beyond the simple DPWMA and DPWMB waveforms already discussed – DPWMC, the Edge Generation Module, and the IntraMux.

DPWMC is a signal inside the DPWM logic. It goes high at the Blanking A begin time, and low at the Blanking A end time.

The Edge Gen module takes DPWMA and DPWMB from its own DPWM module, and the next one, and uses them to generate edges for two outputs. For DPWM3, the DPWM0 is considered to be the next DPWM. Each edge (rising and falling for DPWMA and DPWMB) has 8 options which can cause it.

The options are:

0 = DPWM(n) A Rising edge
1 = DPWM(n) A Falling edge
2 = DPWM(n) B Rising edge
3 = DPWM(n) B Falling edge
4 = DPWM(n+1) A Rising edge
5 = DPWM(n+1) A Falling edge
6 = DPWM(n+1) B Rising edge
7 = DPWM(n+1) B Falling edge

Where “n" is the numerical index of the DPWM module of interest. For example n=1 refers to DPWM1.

The Edge Gen is controlled by the DPWMEDGEGEN register. It also has an enable/disable bit.

The IntraMux is controlled by the Auto Config registers. Intra Mux is short for intra multiplexer. The IntraMux takes signals from multiple DPWMs and from the Edge Gen and combines them logically to generate DPWMA and DPWMB signals This is useful for topologies like phase-shifted full bridge, especially when they are controlled with automatic mode switching. Of course, it can all be disabled, and DPWMA and DPWMB will be driven as described in the sections above. If the Intra Mux is enabled, high resolution must be disabled, and DPWM edge resolution goes down to 4 ns.

Here is a drawing of the Edge Gen/Intra Mux:

UCD3138128 UCD3138A64 gen_intra_mux_lusap2.gif

Figure 16. Edge Generation / IntraMux

Here is a list of the IntraMux modes for DPWMA:

0 = DPWMA(n) pass through (default)
1 = Edge-gen output, DPWMA(n)
2 = DPWNC(n)
3 = DPWMB(n) (Crossover)
4 = DPWMA(n+1)
5 = DPWMB(n+1)
6 = DPWMC(n+1)
7 = DPWMC(n+2)
8 = DPWMC(n+3)

and for DPWMB:

0 = DPWMB(n) pass through (default)
1 = Edge-gen output, DPWMB(n)
2 = DPWNC(n)
3 = DPWMA(n) (Crossover)
4 = DPWMA(n+1)
5 = DPWMB(n+1)
6 = DPWMC(n+1)
7 = DPWMC(n+2)
8 = DPWMC(n+3)

The DPWM number wraps around just like the Edge Gen unit. For DPWM3 the following definitions apply:

DPWM(n)	DPWM3
DPWM(n+1)	DPWM0
DPWM(n+2)	DPWM1
DPWM(n+3)	DPWM2

9.3.5 Filter

The UCD3138x filter is a PID filter with many enhancements for power supply control. Some of its features include:

Traditional PID Architecture
Programmable non-linear limits for automated modification of filter coefficients based on received EADC error
Multiple coefficient sets fully configurable by firmware
Full 24-bit precision throughout filter calculations
Programmable clamps on integrator branch and filter output
Ability to load values into internal filter registers while system is running
Ability to stall calculations on any of the individual filter branches
Ability to turn off calculations on any of the individual filter branches
Duty cycle, resonant period, or phase shift generation based on filter output.
Flux balancing
Voltage feed forward

Here is the first section of the Filter :

UCD3138128 UCD3138A64 PID_filter_stages_lusap2.gif

Figure 17. First Section of the Filter

The filter input, Xn, generally comes from a front end. Then there are three branches, P, I. and D. Note that the D branch also has a pole, Kd Alpha. Clamps are provided both on the I branch and on the D alpha pole.

The filter also supports a nonlinear mode, where up to 7 different sets of coefficients can be selected depending on the magnitude of the error input Xn. This can be used to increase the filter gain for higher errors to improve transient response.

Here is the output section of the filter (S0.23 means that there is 1 sign bit, 0 integer bits and 23 fractional bits).:

UCD3138128 UCD3138A64 flt2a_section2_lusap2.gif

Figure 18. Output Section of the Filter

This section combines the P, I, and D sections, and provides for saturation, scaling, and clamping.

There is a final section for the filter, which permits its output to be matched to the DPWM:



	Figure 19. Final Section for the Filter

This permits the filter output to be multiplied by a variety of correction factors to match the DPWM Period, to provide for Voltage Feed Forward, or for other purposes. After this, there is another clamp. For resonant mode, the filter can be used to generate both period and duty cycle.

9.3.5.1 Loop Multiplexer

The Loop Mux controls interconnections between the filters, front ends, and DPWMs. Any filter, front end, and DPWM can be combined in a variety of configurations.

It also controls the following connections:

DPWM to Front End
Front End DAC control from Filters or Constant Current/Constant Power Module
Filter Special Coefficients and Feed Forward
DPWM synchronization
Filter to DPWM

The following control modules are configured in the Loop Mux:

Constant Power/Constant Current
Cycle Adjustment (Current and flux balancing)
Global Period
Light Load (Burst Mode)
Analog Peak Current Mode

9.3.5.2 Fault Multiplexer

In order to allow a flexible way of mapping several fault triggering sources to all the DPWMs channels, the UCD3138x provides an extensive array of multiplexers that are united under the name Fault Mux module.

The Fault Mux Module supports the following types of mapping between all the sources of fault and all the different fault response mechanisms inside each DPWM module.

Many fault sources may be mapped to a single fault response mechanism. For instance an analog comparator in charge of over voltage protection, a digital comparator in charge of over current protection and an external digital fault pin can be all mapped to a Fault-A signal connected to a single FAULT MODULE and shut down DPWM1-A.
A single fault source can be mapped to many fault response mechanisms inside many DPWM modules. For instance an analog comparator in charge of over current protection can be mapped to DPWM-0 through DPWM-3 by way of several fault modules.
Many fault sources can be mapped to many fault modules inside many DPWM modules.

UCD3138128 UCD3138A64 Fault_mux_dwg_lusap2.gif

Figure 20. Fault Mux Module

The Fault Mux Module provides a multitude of fault protection functions within the UCD3138x high-speed loop (Front End Control, Filter, DPWM and Loop Mux modules). The Fault Mux Module allows highly configurable fault generation based on digital comparators, high-speed analog comparators and external fault pins. Each of the fault inputs to the DPWM modules can be configured to one or any combination of the fault events provided in the Fault Mux Module.

Each one of the DPWM engines has four fault modules. The modules are called CBC fault module, AB fault module, A fault module and B fault module.

The internal circuitry in all the four fault modules is identical, and the difference between the modules is limited to the way the modules are attached to the DPWMs.

UCD3138128 UCD3138A64 fault_module_lusap2.gif

Figure 21. Fault Module

All fault modules provide immediate fault detection but only once per DPWM switching cycle. Each one of the fault modules own a separate max_count and the fault flag will be set only if sequential cycle-by-cycle fault count exceeds max_count.

Once the fault flag is set, DPWMs need to be disabled by DPWM_EN going low in order to clear the fault flags. Please note, all four Fault Modules share the same DPWM_EN control, all fault flags (output of Fault Modules) will be cleared simultaneously.

All four Fault Modules share the same global FAULT_EN as well. Therefore a specific Fault Module cannot be enabled/ disabled separately.

UCD3138128 UCD3138A64 cyc_cyc_lusap2.gif

Figure 22. Cycle-By-Cycle Block

Unlike Fault Modules, only one Cycle by Cycle block is available in each DPWM module.

The Cycle by Cycle block works in conjunction with CBC Fault Module and enables DPWM reaction to signals arriving from the Analog Peak current mode (PCM) module.

The Fault Mux Module supports the following basic functions:

4 digital comparators with programmable thresholds and fault generation
Configuration for 7 high speed analog comparators with programmable thresholds and fault generation
External GPIO detection control with programmable fault generation
Configurable DPWM fault generation for DPWM Current Limit Fault, DPWM Over-Voltage Detection Fault, DPWM A External Fault, DPWM B External Fault and DPWM IDE Flag
Clock Failure Detection for High and Low Frequency Oscillator blocks
Discontinuous Conduction Mode Detection

UCD3138128 UCD3138A64 fault_mux_bd_lusap2.gif

Figure 23. Fault Mux Block Diagram

9.3.6 Communication Ports

9.3.6.1 SCI (UART) Serial Communication Interface

A maximum of two independent Serial Communication Interface (SCI) or Universal Asynchronous Receiver/Transmitter (UART) interfaces are included within the device for asynchronous start-stop serial data communication (see the pin out sections for details). Each interface has a 24 bit pre-scaler for supporting programmable baud rates, a programmable data word and stop bit options. Half or full duplex operation is configurable through register bits. A loop back feature can also be setup for firmware verification. Both SCI-TX and SCI-RX pin sets can be used as GPIO pins when the peripheral is not being used.

9.3.6.2 PMBUS/I²C

The UCD3138x has two independent interfaces which both support PMBus and I²C in master and slave modes. Only one of the interfaces has control of the address pin current sources as well as support for the optional Control and Alert lines described in the PMBus specification. Other than these differences, the interfaces are identical.

The PMBus/I²C interface is designed to minimize the processor overhead required for interface. It can automatically detect and acknowledge addresses. It handles start and stop conditions automatically, and can clock stretch until the processor has time to poll the PMBus status. It will automatically receive and send up to 4 bytes at a time. It can automatically verify and generate a PEC. This means that a write byte command can be received by the processor with only one function call. There is no need for any interrupts at all with this PMBus/I²C interface. If it is polled every few milliseconds, it will work perfectly.

The interface also supports automatic ACK of two independent addresses. If both PMBus/I²C interfaces are used at the same time a total of 4 independent addresses can be automatically detected.

Example: PMBus Address Decode via ADC12 Reading

The user can allocate 2 pins of the 12-bit ADC input channels, AD_00 and AD_01, for PMBus address decoding. At power-up the device applies I_BIAS to each address detect pin and the voltage on that pin is captured by the internal 12-bit ADC.

UCD3138128 UCD3138A64 PMBus_add_lusap2.gif

Figure 24. PMBUS Address Detection Method

PMBus/I²C address 0x7E is a reserved address and should not be used in a system using the UCD3138x. This address is used for manufacturing test.

9.3.6.3 SPI

The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communication between the UCD3138x and external peripherals. Typical applications include an interface to external I/O or peripheral expansion via devices such as shift registers, display drivers, SPI EPROMs and analog-to-digital converters. The SPI allows serial communication with other SPI devices through a 3-pin or 4-pin mode interface. The SPI typically is configured as a master for communicating to external EEPROM.

UCD3138128 UCD3138A64 SPI-TIMING-03-2013-JPL.gif

Figure 25. SPI Timing Diagram

9.3.7 Real Time Clock

The UCD3138x has an internal real time clock (RTC) function that can track time in seconds, minutes, hours and days. This function requires an external precision 10 MHz clock.

Firmware writable time/day register which tracks the total number of days.
- The day counter will be able to count 4 years worth of days.
- Years and months and leap year calculation must be calculated in firmware.

Firmware programmable frequency correction of ±200 ppm in 0.8 ppm steps

The RTC function can provide interrupts to the IRQ or FIQ at 1, 10, 30, and 60 second intervals.

The clock from the RTC driver can be driven to an external pin through an internal multiplexor

The clock for the RTC function can come from an external clock through a dedicated GPIO pin.

9.3.8 Timers

External to the Digital Power Peripherals there are 3 different types of timers in UCD3138x. They are the 24-bit timer, 16-bit timer and the watchdog timer

9.3.8.1 24-Bit Timer

There is one 24 bit timer which runs off the Interface Clock. It can be used to measure the time between two events, and to generate interrupts after a specific interval. Its clock can be divided down by an 8-bit pre-scalar to provide longer intervals. The timer has two compare registers (Data Registers). Both can be used to generate an interrupt after a time interval. . Additionally, the timer has a shadow register (Data Buffer register) which can be used to store CPU updates of the compare events while still using the timer. The selected shadow register update mode happens after the compare event matches.

The two capture pins TCAP0 and TCAP1 are inputs for recording a capture event. A capture event can be set either to rising, falling, or both edges of the capture pin signal. Upon this event, the counter value is stored in the corresponding capture data register. Five Interrupts from the 24 bit timer can be set, which are the counter rollover event (overflow), capture events 0 and 1, and the two comparison match events. Each interrupt can be disabled or enabled.

9.3.8.2 16-Bit PWM Timers

There are four 16 bit counter PWM timers which run off the Interface Clock and can further be divided down by a 8-bit pre-scaler to generate slower PWM time periods. Each timer has two compare registers (Data Registers) for generating the PWM set/unset events. Additionally, each timer has a shadow register (Data Buffer register) which can be used to store CPU updates of compare events while still using the timer. The selected shadow register update mode happens after the compare event matches.

The counter reset can be configured to happen on a counter roll over, a compare equal event, or by a software controlled register. Interrupts from the PWM timer can be set due to the counter rollover event (overflow) or by the two comparison match events. Each comparison match and the overflow interrupts can be disabled or enabled.

Upon an event comparison, the PWM pin can be configured to set, clear, toggle or have no action at the output. The value of PWM pin output can be read for status or simply configured as General Purpose I/O for reading the value of the input at the pin.

9.3.8.3 Watchdog Timer

A watchdog timer is provided on the device for ensuring proper firmware loop execution. The timer is clocked off of a separate low speed oscillator source. If the timer is allowed to expire, a reset condition is issued to the ARM processor. The watchdog is reset by a simple CPU write bit to the watchdog key register by the firmware routine. On device power-up the watchdog is disabled. Yet after it is enabled, the watchdog cannot be disabled by firmware. Only a device reset can put this bit back to the default disabled state. A half timer flag is also provided for status monitoring of the watchdog.

9.3.9 General Purpose ADC12

The ADC12 is a 12 bit, high speed analog to digital converter, equipped with the following options:

Typical conversion speed of 267 ksps
Conversions can consist from 1 to 16 ADC channel conversions in any desired sequence
Post conversion averaging capability, ranging from 4X, 8X, 16X or 32X samples
Configurable triggering for ADC conversions from the following sources: firmware, DPWM rising edge, ADC_EXT_TRIG pin or Analog Comparator results
Interrupt capability to embedded processor at completion of ADC conversion
Six digital comparators on the first 6 channels of the conversion sequence using either raw ADC data or averaged ADC data
Two 10 µA current sources for excitation of PMBus addressing resistors
Dual sample and hold for accurate power measurement
Internal temperature sensor for temperature protection and monitoring

The control module (ADC12 Contol Block Diagram) contains the control and conversion logic for auto-sequencing a series of conversions. The sequencing is fully configurable for any combination of 16 possible ADC channels through an analog multiplexer embedded in the ADC12 block. Once converted, the selected channel value is stored in the result register associated with the sequence number. Input channels can be sampled in any desired order or programmed to repeat conversions on the same channel multiple times during a conversion sequence. Selected channel conversions are also stored in the result registers in order of conversion, where the result 0 register is the first conversion of a 16-channel sequence and result 15 register is the last conversion of a 16-channel sequence. The number of channels converted in a sequence can vary from 1 to 16.

Unlike EADC0 through EADC2, which are primarily designed for closing high speed compensation loops, the ADC12 is not usually used for loop compensation purposes. The EADC converters have a substantially faster conversion rate, thus making them more attractive for closed loop control. The ADC12 features make it best suited for monitoring and detection of currents, voltages, temperatures and faults. Please see the Typical Characteristics plots for the temperature variation associated with this function.

UCD3138128 UCD3138A64 ADC12_contrl_blk_lusap2.gif

Figure 26. ADC12 Control Block Diagram

9.3.10 Miscellaneous Analog

The Miscellaneous Analog Control (MAC) Registers are a catch-all of registers that control and monitor a wide variety of functions. These functions include device supervisory features such as Brown-Out and power saving configuration, general purpose input/output configuration and interfacing, internal temperature sensor control and current sharing control.

The MAC module also provides trim signals to the oscillator and AFE blocks. These controls are usually used at the time of trimming at manufacturing; therefore this document will not cover these trim controls.

9.3.11 Brownout

Brownout function is used to determine if the device supply voltage is lower than a threshold voltage, a condition that may be considered unsafe for proper operation of the device.

The brownout threshold is higher than the reset threshold voltage; therefore, when the supply voltage is lower than brownout threshold, it still does not necessarily trigger a device reset.

The brownout interrupt flag can be polled or alternatively can trigger an interrupt to service such case by an interrupt service routine. Please see the Power On Reset (POR) / Brown Out Reset (BOR) section.

9.3.12 Global I/O

Up to 32 pins in UCD3138x can be configured in the Global I/O register to serve as a general purpose input or output pins (GPIO). This includes all digital input or output pins except for the RESET pin.

The pins that cannot be configured as GPIO pins are the supply pins, ground pins, ADC-12 analog input pins, EADC analog input pins and the RESET pin. Additional digital pins not listed in this register can be configured through their local configuration registers.

There are two ways to configure and use the digital pins as GPIO pins:

Through the centralized Global I/O control registers.
Through the distributed control registers in the specific peripheral that shares it pins with the standard GPIO functionality.

The Global I/O registers offer full control of:

Configuring each pin as a GPIO.
Setting each pin as input or output.
Reading the pin’s logic state, if it is configured as an input pin.
Setting the logic state of the pin, if it is configured as an output pin.
Connecting pin/pins to high rail through internal push/pull drivers or external pull up resistors.

The Global I/O registers include Global I/O EN register, Global I/O OE Register, Global I/O Open Drain Control Register, Global I/O Value Register and Global I/O Read Register.

The following is showing the format of Global I/O EN Register (GLBIOEN) as an example:

BIT NUMBER	31:0
Bit Name	GLOBAL_IO_EN
Access	R/W
Default	0000_0000_0000_0000_0000_0000_0000_0000

Bits 29-0: GLOBAL_IO_EN – This register enables the global control of digital I/O pins
0 = Control of IO is done by the functional block assigned to the IO (Default)
1 = Control of IO is done by Global IO registers.

BIT	PIN_NAME	PIN NUMBER
BIT	PIN_NAME	UCD3138x
31	PWM2	11
30	PWM3	12
29	FAULT3	55
28	ADC_EXT_TRIG	14
27	TCK	45
26	TDO	46
25	TMS	48
24	TDI	47
23	SCI_TX1	37
22	SCI_TX0	35
21	SCI_RX1	38
20	SCI_RX0	36
19	TCAP0	49
18	PWM1	40
17	PWM0	39
16	TCAP1	13
15	I2C_DATA	20
14	PMBUS_CTRL	18
13	PMBUS_ALERT	17
12	EXT_INT	42
11	FAULT2	54
10	FAULT1	44
9	FAULT0	43
8	SYNC	34
7	DPWM3B	29
6	DPWM3A	28
5	DPWM2B	27
4	DPWM2A	26
3	DPWM1B	25
2	DPWM1A	24
1	DPWM0B	23
0	DPWM0A	22

9.3.13 Temperature Sensor Control

Temperature sensor control register provides internal temperature sensor enabling and trimming capabilities. The internal temperature sensor is disabled by default.

UCD3138128 UCD3138A64 temp_sensor_SLUSBZ8.gif

Figure 27. Internal Temp Sensor

Temperature sensor is calibrated at room temperature (25 °C) via a calibration register value.

The temperature sensor is measured using ADC12 (via Ch15). The temperature is then calculated using a mathematical formula involving the calibration register (this effectively adds a delta to the ADC measurement).

The temperature sensor can be enabled or disabled.

9.3.14 I/O Mux Control

I/O Mux Control register may be used in order to choose a single specific functionality that is desired to be assigned to a physical device pin for your application. See the UCD3138x programmer's manual for details on the available configurations.

9.3.15 Current Sharing Control

UCD3138x provides three separate modes of current sharing operation.

Analog bus current sharing
PWM bus current sharing
Master/Slave current sharing
AD02 has a special ESD protection mechanism that prevents the pin from pulling down the current-share bus if power is missing from the UCD3138x

The simplified current sharing circuitry is shown in the drawing below. The digital pulse connected to SW3 transforms SW3 into a pulse-width-modulated current source. Details on the frequency and resolution of this feature are in the digital power fusion peripherals manual.

UCD3138128 UCD3138A64 Current_sharing_dwg_lusap2.gif

Figure 28. Simplified Current Sharing Circuitry

CURRENT SHARING MODE	CS_MODE	EN_SW1	EN_SW2	DPWM
Off or Slave Mode (3-state)	00 (default)	0	0	0
PWM Bus	01	1	0	ACTIVE
Off or Slave Mode (3-state)	10	0	0	0
Analog Bus or Master	11	0	1	0

The period and the duty of 8-bit PWM current source and the state of the SW1 and SW2 switches can be controlled through the current sharing control register (CSCTRL).

9.3.16 Temperature Reference

The temperature reference register (TEMPREF) provides the ADC12 count when ADC12 measures the internal temperature sensor (channel 15) during the factory trim and calibration.

This information can be used by different periodic temperature compensation routines implemented in the firmware. But it should not be overwritten by firmware, otherwise this factory written value will be lost until the device is reset.

9.4 Device Functional Modes

9.4.1 DPWM Modes Of Operation

The DPWM is a complex logic system which is highly configurable to support several different power supply topologies. The discussion below will focus primarily on waveforms, timing and register settings, rather than on logic design.

The DPWM is centered on a period counter, which counts up from 0 to PRD, and then is reset and starts over again.

The DPWM logic causes transitions in many digital signals when the period counter hits the target value for that signal.

9.4.1.1 Normal Mode

In Normal mode, the Filter output determines the pulse width on DPWM A. DPWM B fits into the rest of the switching period, with a dead time separating it from the DPWM A on-time. It is useful for buck topologies, among others. Here is a drawing of the Normal Mode waveforms:

UCD3138128 UCD3138A64 normal2_closed_loop_lusap2.gif

Figure 29. Normal Mode - Closed Loop

Cycle adjust A can be used to adjust pulse widths on individual phases of a multi-phase system. This can be used for functions like current balancing. The Adaptive Sample Triggers can be used to sample in the middle of the on-time (for an average output), or at the end of the on-time (to minimize phase delay) The Adaptive Sample Register provides an offset from the center of the on-time. This can compensate for external delays, such as MOSFET and gate driver turn on times.

Blanking A-Begin and Blanking A-End can be used to blank out noise from the MOSFET turn on at the beginning of the period (DPWMA rising edge). Blanking B could be used at the turn off time of DPWMB. The other edges are dynamic, so blanking is more difficult.

Cycle Adjust B has no effect in Normal Mode.

9.4.1.2 Phase Shifting

In most modes, it is possible to synchronize multiple DPWM modules using the phase shift signal. The phase shift signal has two possible sources. It can come from the Phase Trigger Register. This provides a fixed value, which is useful for an application like interleaved PFC.

The phase shift value can also come from the filter output. In this case, the changes in the filter output causes changes in the phase relationship of two DPWM modules. This is useful for phase shifted full bridge topologies.

The following figure shows the mechanism of phase shift:

UCD3138128 UCD3138A64 phase2_shift_lusap2.gif

Figure 30. Phase Shifting

9.4.1.3 DPWM Multiple Output Mode

Multi mode is used for systems where each phase has only one driver signal. It enables each DPWM peripheral to drive two phases with the same pulse width, but with a time offset between the phases, and with different cycle adjusts for each phase.

The Multi-Mode diagram is shown in Figure 31.

UCD3138128 UCD3138A64 Multi_Mode_Closed_Loop_2_SLUSB72.gif

Figure 31. DPWM Multi-Mode Close Loop

Event 2 and Event 4 are not relevant in Multi mode.

DPWMB can cross over the period boundary safely, and still have the proper pulse width, so full 100% pulse width operation is possible. DPWMA cannot cross over the period boundary.

Since the rising edge on DPWM B is also fixed, Blanking B-Begin and Blanking B-End can be used for blanking this rising edge.

And, of course, Cycle Adjust B is usable on DPWM B.

9.4.1.4 DPWM Resonant Mode

This mode provides a symmetrical waveform where DPWMA and DPWMB have the same pulse width. As the switching frequency changes, the dead times between the pulses remain the same.

The equations for this mode are designed for a smooth transition from PWM mode to resonant mode, as described in the LLC Example section. Here is a diagram of this mode:

UCD3138128 UCD3138A64 resonant2_mode_lusap2.gif

Figure 32. DPWM Resonant Symmetrical Mode

The Filter has two outputs, Filter Duty and Filter Period. In this case, the Filter is configured so that the Filter Period is twice the Filter Duty. So if there were no dead times, each DPWM pin would be on for half of the period. For dead time handling, the average of the two dead times is subtracted from the Filter Duty for both DPWM pins. Therefore, both pins will have the same on-time, and the dead times will be fixed regardless of the period. The only edge which is fixed relative to the start of the period is the rising edge of DPWM A. This is the only edge for which the blanking signals can be used easily.

9.4.2 Triangular Mode

Triangular mode provides a stable phase shift in interleaved PFC and similar topologies. In this case, the PWM pulse is centered in the middle of the period, rather than starting at one end or the other. In Triangular Mode, only DPWM-B is available. Here is a diagram for Triangular Mode:

UCD3138128 UCD3138A64 triangular2_mode_lusap2.gif

Figure 33. Triangular Mode

All edges are dynamic in triangular mode, so fixed blanking is not that useful. The adaptive sample trigger is not needed. It is very easy to put a fixed sample trigger exactly in the center of the FET on-time, because the center of the on-time does not move in this mode.

9.4.3 Leading Edge Mode

Leading edge mode is similar to Normal mode, reversed in time. The DPWM A falling edge is fixed, and the rising edge moves to the left, or backwards in time, as the filter output increases. The DPWM B falling edge stays ahead of the DPWMA rising edge by a fixed dead time. Here is a diagram of the Leading Edge Mode:

UCD3138128 UCD3138A64 leading2_edge_lusap2.gif

Figure 34. Leading Edge Mode

As in the Normal mode, the two edges in the middle of the period are dynamic, so the fixed blanking intervals are mainly useful for the edges at the beginning and end of the period.

9.5 Register Maps

9.5.1 CPU Memory Map And Interrupts

When the device comes out of power-on-reset, the data memories are mapped to the processor as follows:

9.5.1.1 Memory Map (After Reset Operation)

ADDRESS	SIZE (BYTES)	MODULE
0x0000_0000 – 0x0003_FFFF In 32 repeated blocks of 8 k each	32 X 8 k	Boot ROM
0x0004_0000 – 0x0004_7FFF	32 k	Program Flash 0
0x0004_8000 – 0x0004_FFFF	32 k	Program Flash 1
0x0005_0000_0x0005_7FFF	32 k	Program Flash 2
0x0005_0000_0x0005_7FFF	32 k	Program Flash 3
0x0006_9800 – 0x0006_9FFF	2 k	Data Flash
0x0006_A000 – 0x0006_BFFF	8 k	Data RAM

9.5.1.2 Memory Map (Normal Operation)

Just before the boot ROM program gives control to flash program, the ROM configures the memory as follows:

ADDRESS	SIZE (BYTES)	MODULE
0x0002_0000 – 0x0002_1FFF	8 k	Boot ROM
0x0000_0000 – 0x00000_07FFF	32 k	Program Flash 0 (or 1)
0x0000_8000 – 0x08000_0FFFF	32 k	Program Flash 1 (or 0)
0x0000_8000 - 0x10000_17FFF	32 k	Program Flash 2 (or 0 for UCD3138128 only)
0x0000_8000 - 0x18000_1FFFF	32 k	Program Flash 3 (or 1 for UCD3138128 only)
0x0006_9800 – 0x0006_9FFF	2 k	Data Flash
0x0006_A000 – 0x0006_BFFF	8 k	Data RAM

9.5.1.3 Memory Map (System And Peripherals Blocks)

ADDRESS	SIZE	MODULE
0x0012_0000 - 0x0012_00FF	256	Loop Mux
0x0013_0000 - 0x0013_00FF	256	Fault Mux
0x0014_0000 - 0x0014_00FF	256	ADC
0x0015_0000 - 0x0015_00FF	256	DPWM 3
0x0016_0000 - 0x0016_00FF	256	Filter 2
0x0017_0000 - 0x0017_00FF	256	DPWM 2
0x0018_0000 - 0x0018_00FF	256	Front End/Ramp Interface 2
0x0019_0000 - 0x0019_00FF	256	Filter 1
0x001A_0000 - 0x001A_00FF	256	DPWM 1
0x001B_0000 – 0x001B_00FF	256	Front End/Ramp Interface 1
0x001C_0000 - 0x001C_00FF	256	Filter 0
0x001D_0000 - 0x001D_00FF	256	DPWM 0
0x001E_0000 - 0x001E_00FF	256	Front End/Ramp Interface 0
0xFFF7_E400 - 0xFFF7_34FF	256	RTC
0xFFF7_EC00 - 0xFFF7_ECFF	256	UART 0
0xFFF7_ED00 - 0xFFF7_EDFF	256	UART 1
0xFFF7_F000 - 0xFFF7_F0FF	256	Miscellaneous Analog Control
0xFFF7_F600 - 0xFFF7_F6FF	256	PMBus/I²C Interface (1)
0xFFF7_F700 - 0xFFF7_F7FF	256	PMBus/I²C Interface (2)
0xFFF7_FA00 - 0xFFF7_FAFF	256	GIO
0xFFF7_FD00 - 0xFFF7_FDFF	256	Timer
0xFFFF_FD00 - 0xFFFF_FDFF	256	MMC
0xFFFF_FE00 - 0xFFFF_FEFF	256	DEC
0xFFFF_FF20 - 0xFFFF_FF37	23	CIM
0xFFFF_FFD0 - 0xFFFF_FFEC	28	SYS

The registers and bit definitions inside the System and Peripheral blocks are detailed in the programmer’s manuals.

9.5.2 Boot ROM

The device incorporates a 8 kB boot ROM. This boot ROM includes support for:

Program download through the PMBus
Device initialization
Examining and modifying registers and memory
Verifying and executing program flash automatically
Jumping to a customer defined boot program
Checksum evaluation to support using the program flash as a single 64 kB block or as 2-32 kB blocks.

The Boot ROM is entered automatically on device reset. It initializes the device and then performs checksums on the program flash. If the first 2 kB of program FLASH 0 has a valid checksum, the program branches to location 0 in Program FLASH 0. This permits the use of a custom boot program. If the first checksum fails, it performs some additional checksum calculations to determine where the valid program is located. This permits full automated program memory checking, when there is no need for a custom boot program. The complete decision tree is located in Figure 35. Additionally, the part can support two separate programs in block 0 and block 1 through a custom boot-flash routine.

UCD3138128 UCD3138A64 ck_sum_3138A64_SLUSBZ8.gif

Figure 35. Check Sum Evaluation Flowchart, 64 kB

UCD3138128 UCD3138A64 ck_sum_3138128_SLUSBZ8.gif

Figure 36. Check Sum Evaluation Flowchart, 128 kB

If none of the checksums are valid, the Boot ROM stays in control, and accepts commands via the PMBus interface. These functions can be used to read and write to all memory locations in the device. Typically they are at address 11 and are used to download a program to Program Flash, and to command its execution.

9.5.3 Customer Boot Program

As described above, it is possible to generate a user boot program using 2 kB or more of the Program Flash. This can support things which the Boot ROM does not support, including:

Program download via UART – useful especially for applications where the UCD3138A64 or UCD3138128 is isolated from the host (e.g., PFC)
Encrypted download – useful for code security in field updates.
PMBus download at different addresses
Different command formats

9.5.4 Flash Management

The device offers a variety of features providing for easy prototyping and easy flash programming. At the same time, high levels of security are possible for production code, even with field updates. Standard firmware will be provided for storing multiple copies of system parameters in data flash. This minimizes the risk of losing information if data-flash programming is interrupted.

9.6 Synchronous Rectifier MOSFET Ramp And IDE Calculation

The device has built in logic for optimizing the performance of the synchronous rectifier MOSFETs. This comes in two forms:

Synchronous Rectifier MOSFET ramp for softly turning on and off the MOSFETs
Ideal Diode Emulation (IDE) calculation

When starting up a power supply, It is not uncommon for there to already be a voltage present on the output – this is called pre-bias. It can be very difficult to calculate the ideal synchronous rectifier MOSFET on-time for this case. If it is not calculated correctly, it may pull down the pre-bias voltage, causing the power supply to sink current. To avoid this, the synchronous rectifier MOSFETs are not turned on until after the power supply has ramped up to the nominal output voltage. The synchronous rectifier MOSFETs are then turned on slowly in order to avoid an output voltage glitch. The synchronous rectifier MOSFET ramp logic can be used to turn them on at a rate well below the bandwidth of the filter.

In discontinuous mode, the ideal on-time for the synchronous rectifier MOSFETs is a function of V_in, V_out, and the primary side duty cycle (D). The IDE logic in the UCD3138x takes V_in and V_out data from the firmware and combines it with D data from the filter hardware. It uses this information to calculate the ideal on-time for the synchronous rectifier MOSFETs.