ZHCSJQ1D November 2010 – April 2019 UCD90160
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4
Device Functional Modes
- 7.4.1 Power-Supply Sequencing
- 7.4.2 Pin-Selected Rail States
- 7.4.3 Voltage Monitoring
- 7.4.4 Fault Responses and Alert Processing
- 7.4.5 Shut Down All Rails and Sequence On (Resequence)
- 7.4.6 GPIOs
- 7.4.7 GPO Control
- 7.4.8 GPO Dependencies
- 7.4.9 GPI Special Functions
- 7.4.10 Power-Supply Enables
- 7.4.11 Cascading Multiple Devices
- 7.4.12 PWM Outputs
- 7.4.13 Programmable Multiphase PWMs
- 7.4.14 Margining
- 7.4.15 System Reset Signal
- 7.4.16 Watch Dog Timer
- 7.4.17 Run Time Clock
- 7.4.18 Data and Error Logging to Flash Memory
- 7.4.19 Brownout Function
- 7.4.20 PMBus Address Selection
- 7.5 Programming
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文档支持
- 12机械、封装和可订购信息
6.6 Timing Requirements: I2C/SMBus/PMBus
TA = –40°C to 85°C, 3 V < VDD < 3.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| FSMB | SMBus/PMBus operating frequency | Slave mode, SMBC 50% duty cycle | 10 | 400 | kHz | |
| FI2C | I2C operating frequency | Slave mode, SCL 50% duty cycle | 10 | 400 | kHz | |
| t(BUF) | Bus free time between start and stop | 1.3 | μs | |||
| t(HD:STA) | Hold time after (repeated) start | 0.6 | μs | |||
| t(SU:STA) | Repeated-start setup time | 0.6 | μs | |||
| t(SU:STO) | Stop setup time | 0.6 | μs | |||
| t(HD:DAT) | Data hold time | Receive mode | 0 | ns | ||
| t(SU:DAT) | Data setup time | 100 | ns | |||
| t(TIMEOUT) | Error signal/detect | See(1) | 35 | ms | ||
| t(LOW) | Clock low period | 1.3 | μs | |||
| t(HIGH) | Clock high period | See (2) | 0.6 | μs | ||
| t(LOW:SEXT) | Cumulative clock low slave extend time | See (3) | 25 | ms | ||
| tf | Clock/data fall time | See (4) | 300 | ns | ||
| tr | Clock/data rise time | See (5) | 300 | ns | ||
| Cb | Total capacitance of one bus line | 400 | pF | |||
(1) The device times out when any clock low exceeds t(TIMEOUT).
(2) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
(3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) Fall time tf = 0.9 VDD to (VILMAX – 0.15)
(5) Rise time tr = (VILMAX – 0.15) to (VIHMIN + 0.15)
Figure 1. I2C/SMBus Timing Diagram 
Figure 2. Bus Timing in Extended Mode