米6体育平台手机版

ZHCSFI3B August 2016 – May 2019 UCD90320

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

ZWS|169
- MPBGAK4B

散热焊盘机械数据 (封装 | 引脚)

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7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENT
I_V33	Supply Current	V_V33D = V_V33A = 3.3 V		31.4	54.9	mA
ON-CHIP LOW DROP-OUT (LDO) REGULATOR
C_LDO	External filter capacitor size for internal power supply⁽¹⁾		2.5		4	µF
V_LDO	LDO output voltage		1.08	1.2	1.32	V
I_INRUSH	Inrush current		50		250	mA
ANALOG-TO-DIGITAL CONVERTER (ADC)⁽²⁾⁽³⁾
V33A	ADC supply voltage		2.97	3.3	3.63	V
AVSS	ADC ground voltage			0		V
C_V33A	Voltage reference decoupling capacitance between V33A and AVSS (if using internal reference) ⁽⁴⁾			1.01		µF
V_REFA+	Positive external voltage reference on VREFA+ pin		2.4		3	V
V_REF–	Negative external voltage reference on VREF– pin		V_AVSS	AVSS	0.3	V
I_REF	Current on VREF+ pin input	External V_REF+ = 3.3 V		330.5	440	µA
C_REF	Voltage reference decoupling capacitance between VREFA+ and VREFA– (if using external reference)⁽⁴⁾			1.01		µF
V_ADCIN	Analog input range, internal reference⁽⁵⁾		0		V33A	V
V_ADCIN	Analog input range, external reference⁽⁶⁾		V_VREFA–		V_VREFA+	V
I_L	ADC input leakage current				2	µA
R_ADC	ADC equivalent input resistance				2.5	kΩ
C_ADC	ADC equivalent input capacitance				10	pF
F_CONV	ADC conversion rate (on each ADC channel)⁽¹⁾			1		MSPS
N	ADC resolution			12		bits
E_T	Total unadjusted error, over full input rangea when using internal reference			±10	±30	LSB
E_T	Total unadjusted error, over full input range when using external reference			±2.5	±4	LSB
DIGITAL INPUTS AND OUTPUTS (GPIO, Logic GPO, EN, AND MARGIN PINS)
V_IH	I/O high-level input voltage⁽⁷⁾		0.65 × V_V33D		5.5	V
V_IL	I/O low-level input voltage		0		0.35 × V_V33D	V
V_HYS	I/O input hysteresis		0.2			V
V_OH	I/O high-level output voltage		2.4			V
V_OL	I/O low-level output voltage				0.4	V
I_OH	High-level source current	V_OH = 2.4 V⁽⁸⁾	4			mA
I_OL	Low-level sink current	V_OL = 0.4 V⁽⁸⁾	4			mA
RESET AND BROWNOUT
V33DSlew	Minimum V33D slew rate between 2.8 V and 3.2 V		0.1			V/ms
V_RESET	Supply voltage at which device comes out of reset		2	2.3	2.6	V
V_BOR	Supply voltage at which device enters brownout		2.93	3.02	3.11	V
V_SHDN	Supply voltage at which device shuts down		2.7	2.78	2.87	V
t_RESET	Minimum low-pulse width needed at RESET̅ pin			250		ns
t_IRT	Internal reset time⁽⁹⁾			9	11.5	ms

(1) Connect the capacitor as close as possible to pin D6.

(2) Total of two ADC channels run independently during normal operation.

(3) Total unadjusted error is the maximum error at any one code versus the ideal ADC curve. It includes offset error, gain error, and INL at any given ADC code.

(4) Two capacitors (1.0 µF and 0.01 µF) connected in parallel.

(5) Internal reference is connected directly between V33A and AVSS.

(6) External reference noise level must be under 12 bit (–74 dB) of full scale input, over input bandwidth, measured at VREFA+ - VREFA–.

(7) PMBUS_CNTRL, PMBALERT, MARGIN19 and MARGIN20 pins have V_V33D + 0.3 V as maximum input voltage rating.

(8) I_O specifications reflect the maximum current where the corresponding output voltage meets the V_OH/V_OL thresholds.

(9) If power-loss or brown-out event occurs during an EEPROM program or erase operation, and EEPROM needs to be repaired (which is a rare case), the internal reset time may be longer.