ZHCSFI3B August 2016 – May 2019 UCD90320
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 说明 （续）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4
Device Functional Modes
- 8.4.1 Rail Monitoring Configuration
- 8.4.2 GPI Configuration
- 8.4.3 Rail Sequence Configuration
- 8.4.4 Fault Responses Configuration
- 8.4.5 GPO Configuration
- 8.4.6 Margining Configuration
- 8.4.7 Pin Selected Rail States Configuration
- 8.4.8 Watchdog Timer
- 8.4.9 System Reset Function
- 8.4.10 Cascading Multiple Devices
- 8.4.11 Rail Monitoring
- 8.4.12 Status Monitoring
- 8.4.13 Data and Error Logging to EEPROM Memory
- 8.4.14 Black Box First Fault Logging
- 8.4.15 PMBus Address Selection
- 8.4.16 ADC Reference
- 8.4.17 Device Reset
- 8.4.18 Brownout
- 8.4.19 Internal Fault Management
- 8.5 Device Configuration and Programming
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文档支持
- 13机械、封装和可订购信息
7.7 I2C/PMBus Interface Timing Requirements
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| I1 | t(HD:STA) | Start condition hold time | 450 | ns | ||
| I2 | t(LOW) | Clock low period(1) | 450 | ns | ||
| I3 | tr | Clock rise time and data rise time(2) | See(2) | ns | ||
| I4 | t(HD:DAT) | Data hold time | 25 | ns | ||
| I5 | tf | Clock fall time and data fall time(3) | 112.5 | 125 | ns | |
| I6 | t(HIGH) | Clock high time | 300 | ns | ||
| I7 | t(SU:DAT) | Data setup time | 225 | ns | ||
| I8 | t(SU:STA) | Start condition setup time (repeated start only) | 450 | ns | ||
| I9 | t(SU:STO) | Stop condition setup time | 300 | ns | ||
| I10 | t(DV) | Data valid | 25 | ns | ||
(1) PMBus host must support clock stretching per PMBus Power System Management Protocol Specification Part I General Requirements, Transport and Electrical Interface, Revision 1.2, Section 5.2.6.
(2) Because the I2CSCL signal and the I2CSDA signal operate as open-drain-type signals, which the controller can actively drive only "Low", the time that either signal takes to reach a high level depends on external signal capacitance and pull-up resistor values.
(3) Specified at a nominal 50-pF load.
Figure 1. I2C/PMBus Timing Diagram