ZHCSFI3B August 2016 – May 2019 UCD90320
PRODUCTION DATA.
The UCD90320 device provides accurate closed-loop margining for up to 24 voltage rails. System reliability is improved through four-corner testing during system verification. During four-corner testing, the system operates at the minimum and maximum expected ambient temperature and with each power supply set to the minimum and maximum output voltage, commonly referred to as margining. Margining can be controlled via the PMBus interface using the OPERATION command or by configuring two GPI pins as margin-EN and margin-UP/DOWN inputs. The MARGIN_CONFIG command in the UCD90320 Sequencer and System Health Controller PMBus Command Reference user guide describes several margining options, including ignoring faults while margining and using closed-loop margining to trim the rail output voltage.
The device provides 24 PWM output pins for closed-loop margining. Figure 22 shows the block diagram of margining circuit. An external R-C network converts the PWM pulses into a DC margining voltage. The margining voltage is connected to the power supply feedback node through a resistor. The feedback node voltage is thus slightly pulled up or down by the margining voltage, causing the rail output voltage to change. The UCD90320 device monitors the rail output voltage. The device adjusts the margining PWM duty cycle accordingly such that the rail output voltage is regulated at the margin-high or margin-low voltages defined by the user. Effectively, margin control loop of the UCD90320 device overwrites the DC set point of the margined power supply. The margin control loop is extremely slow in order in order to not interfere with the power supply control loop.
Margining pins can be configured under the Pin Assignment tab, as shown in Figure 23. When not margining, the margin pin can operate in one of three modes:
Tri-state mode sets the margin pin to high-impedance. Active Trim mode performs a continuously trim the DC output voltage. Active Duty Cycle mode provides a user-defined fixed PWM duty cycle as shown in Figure 23.