8.4.17 Device Reset

The UCD90320 device has an integrated power-on reset (POR) circuit which monitors the supply voltage. At power up, the POR detects the V33D pin voltage rise. When the V33D voltage is greater than V_RESET, the device comes out of reset.

The device can be forced into the reset state by an external circuit connected to the RESET̅ pin. A logic-low voltage on this pin for longer than t_RESET sets the device into reset state. The device comes out of reset within t_IRT after RESET̅ is released to logic-high level.

Any time the device comes out of reset, it begins an initialization routine that lasts typically 40 ms. A data flash checksum verification is performed at power up. If the checksum verification does not match, the device configuration settings are cleared , the PMBALERT pin is asserted, and a flag is set in the status register. A fault-log checksum verification in the EEPROM is also performed at power up. Each log entry includes the checksum verification status. Only a corrupted log entry is discarded. During the initialization routine, all I/O pins are held at high impedance state. At the end of initialization, the device begins normal operation as defined by the device configuration.