8.4.5.2 Logic GPO

UCD90320U also has 16 dedicated Logic GPO (LGPO) pins. The configuration window is under Pin Assignment tab, as shown in Figure 19.

Figure 19. Logic GPO Configuration Window (Hardware Configure ► Monitor and GPIO Pins Assignment)

Each LGPO is controlled by an internal Boolean logic builder. Figure 20 shows the configuration interface of the Boolean logic builder. As shown, each Boolean logic builder has a top-level logic gate, which can be configured as AND, OR, or NOR gate with optional time delay. The inputs of the top-level logic gate are two AND paths. Each AND path can select a variety of inputs including GPI states, LGPO states, rails' enable pin states,and rail statuses, as shown in Figure 21. The selectable rail statuses are summarized in Table 3. In Table 3, _LATCH type statuses stay asserted until cleared by a MFR PMBus command or by a specially configured GPI pin shown in Figure 12. See the UCD90320U Sequencer and System Health Controller PMBus Command Reference for complete definitions of rail-status types.

Figure 20. Boolean Logic Builder Interface

Figure 21. AND Path Configuration

The POWER_GOOD status used by GPO evaluation is based on actual monitoring result from AMON or DMON pins. For a rail that does not have a voltage monitor pin, the POWER_GOOD status is used by sequencing purpose only, and is not used by GPO evaluation. Therefore during GPO evaluation, a rail without an AMON or DMON pin never reports POWER_GOOD status.

Each LGPO can be also configured as a simple state machine, as shown in Figure 16. In state machine mode, the top-level logic gate is omitted and only one of the two AND paths is evaluated. The output of the state machine is the result of the active AND path. The evaluation initially starts with AND Path #1. If the evaluation result is TRUE, AND Path #1 remains active until its evaluation result becomes FALSE. When the output associates with AND Path#1 becomes FALSE, AND Path #2 becomes active in the next evaluation cycle. AND Path #2 remains active until its evaluation result becomes TRUE, then AND Path #1 becomes active in the next evaluation cycle. An evaluation cycle is triggered when any input signal to the state machine changes state.

GPO1 to GPO8 outputs are internally synchronized to the same clock edge to enable them to change states together. GPO9 to GPO16 outputs are internally synchronized to enable them to change states together. GPO1 through GPIO8 and GPO9 through GPIO16 outputs status are updated within an time window between approximately 1 µs and 3 µs.