ZHCSJE0 September 2018 UCD90320U
PRODUCTION DATA.
The UCD90320U device verifies the firmware by using a checksum algorithm at each power up. If the checksum does not match, the device resets. If the device continues to reset, the SYNC_CLK pin outputs repeated pulses with an approximate 250-ms pulse width that can be observed externally.
The device performs a configuration checksum verification at power up. If the checksum does not match, the device discards all the configuration data. The PMBALERT pin is asserted and a flag is set in the status register.
A fault-log checksum verification in EEPROM is also performed at power up. Each log entry has a checksum. The device discards corrupted log entries.
If the internal firmware watchdog timer times out, the device resets. If the firmware program is corrupted, the device returns to a known state. This return function is normal, so all of the I/O pins are held in high-impedance while the device is in reset. The process confirms each parameter to ensure it falls within the acceptable range.