ZHCSJE0 September 2018 UCD90320U
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 说明 （续）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4
Device Functional Modes
- 8.4.1 Rail Monitoring Configuration
- 8.4.2 GPI Configuration
- 8.4.3 Rail Sequence Configuration
- 8.4.4 Fault Responses Configuration
- 8.4.5 GPO Configuration
- 8.4.6 Margining Configuration
- 8.4.7 Pin Selected Rail States Configuration
- 8.4.8 Watchdog Timer
- 8.4.9 System Reset Function
- 8.4.10 Cascading Multiple Devices
- 8.4.11 Rail Monitoring
- 8.4.12 Status Monitoring
- 8.4.13 Data and Error Logging to EEPROM Memory
- 8.4.14 Black Box First Fault Logging
- 8.4.15 PMBus Address Selection
- 8.4.16 ADC Reference
- 8.4.17 Device Reset
- 8.4.18 Brownout
- 8.4.19 Internal Fault Management
- 8.4.20 Single Event Upset
- 8.5 Device Configuration and Programming
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文档支持
- 13机械、封装和可订购信息
9.2.1 Design Requirements
UCD90320U requires decoupling capacitors on the V33D, V33A, BPCAP, and (if applicable) VREFA+ pins. The capacitance values for V33A, BPCAP and VREFA+ are specified in the Electrical Characteristics table. Consider these capacitor design configurations as options.
- Three 1-μF X7R ceramic capacitors in parallel with two 0.1-μF X7R ceramic capacitors for BPCAP decoupling
- Two 1-μF X7R ceramic capacitors in parallel with four 0.1-μF X7R ceramic capacitors and two 0.01-μF X7R ceramic capacitors for V33D decoupling
- One 1-μF X7R ceramic capacitor in parallel with one 0.1-μF X7R ceramic capacitor and one 0.01-μF X7R ceramic capacitor for V33A decoupling. A 1-Ω resistor can placed between V33D and V33A to decouple the noise on V33D from V33A.
- One 1-μF X7R ceramic capacitor in parallel with one 0.01-μF X7R ceramic capacitor for VREFA+ decoupling (if used)
- Place decoupling capacitors as close to the device as possible.
- If an application does not use the RESET signal, the RESET pin must be tied to V33D, either by direct connection to the nearest V33D pin (Pin F10), or by a R-C circuit as shown in Figure 39. The R-C circuit in Figure 39 can be also used to delay reset at power up. If an application uses the RESET external pin, the trace of the RESET signal must be kept as short as possible. Be sure to place any components connected to the RESET signal as close to the device as possible.
- TI recommends to maintain at least 200-Ω resistance between a low-impedance analog input and a AMON pin. For example, when monitoring a rail voltage without resistor divider, it is recommended to place a 200-Ω resistor at the AMON pin, as shown in Figure 40.
- PMBus commands(project file , PMBus write script file) method is not recommended for the production programming since GPIO pins may have unexpected behaviors which can disable rails that provide power to device. Data flash hex file or data flash script file shall be used for production programming since GPIO pins are under controlled state.
- It is mandatory that the V33D power shall be stable and no device reset shall be fired during the device programming. Data flash may be corrupted if failed to follow these rules.
Figure 39. RESET Pin With R-C Network 
Figure 40. Example of Analog Inputs