ZHCSFJ6B August   2016  – March 2022 UCD9090A

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C/Smbus/PMBus Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 TI Fusion GUI
      2. 7.3.2 PMBus Interface
      3. 7.3.3 Rail Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power Supply Sequencing
        1. 7.4.1.1 Turn-On Sequencing
        2. 7.4.1.2 Turn-Off Sequencing
        3. 7.4.1.3 Sequencing Configuration Options
      2. 7.4.2  Pin-Selected Rail States
      3. 7.4.3  Monitoring
        1. 7.4.3.1 Voltage Monitoring
        2. 7.4.3.2 Current Monitoring
        3. 7.4.3.3 Remote Temperature Monitoring and Internal Temperature Sensor
        4. 7.4.3.4 Temperature by Host Input
      4. 7.4.4  Fault Responses and Alert Processing
      5. 7.4.5  Shut Down All Rails and Sequence On (Resequence)
      6. 7.4.6  GPIOs
      7. 7.4.7  GPO Control
      8. 7.4.8  GPO Dependencies
        1. 7.4.8.1 GPO Delays
        2. 7.4.8.2 State Machine Mode Enable
      9. 7.4.9  GPI Special Functions
        1. 7.4.9.1 Fault Shutdown Rails
        2. 7.4.9.2 Configured as Sequencing Debug Pin
        3. 7.4.9.3 Configured as Fault Pin
        4. 7.4.9.4 Cold Boot Mode Enable
      10. 7.4.10 Power Supply Enables
      11. 7.4.11 Cascading Multiple Devices
      12. 7.4.12 PWM Outputs
        1. 7.4.12.1 FPWM1-8
        2. 7.4.12.2 PWM1-2
      13. 7.4.13 Programmable Multiphase PWMs
      14. 7.4.14 Margining
        1. 7.4.14.1 Open-Loop Margining
        2. 7.4.14.2 Closed-Loop Margining
      15. 7.4.15 Run Time Clock
      16. 7.4.16 System Reset Signal
      17. 7.4.17 Watch Dog Timer
      18. 7.4.18 Data and Error Logging to Flash Memory
      19. 7.4.19 Brownout Function
      20. 7.4.20 PMBus Address Selection
      21. 7.4.21 Device Reset
      22. 7.4.22 JTAG Interface
      23. 7.4.23 Internal Fault Management and Memory Error Correction (ECC)
    5. 7.5 Programming
      1. 7.5.1 Full Configuration Update While in Normal Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Estimating ADC Reporting Accuracy
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RGZ|48
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

Note:

The number of configurable rails is a maximum of ten. The maximum number of configurable GPIs is eight. The maximum number of configurable boolean logic GPOs is ten.

GUID-75E8A1B4-23B9-4866-AD57-039CC99DAE04-low.gifFigure 5-1 Pin Assignments for the VQFN Package
Figure 5-2 RGZ Package, 48-Pin VQFN With Exposed Thermal Pad (Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
ANALOG MONITOR INPUTS
MON1 1 I Analog input (0 V–2.5 V)
MON2 2 I Analog input (0 V–2.5 V)
MON3 38 I Analog input (0 V–2.5 V)
MON4 39 I Analog input (0 V–2.5 V)
MON5 40 I Analog input (0 V–2.5 V)
MON6 41 I Analog input (0 V–2.5 V)
MON7 42 I Analog input (0 V–2.5 V)
MON8 45 I Analog input (0 V–2.5 V)
MON9 46 I Analog input (0 V–2.5 V)
MON10 48 I Analog input (0 V–2.5 V)
MON11 37 I Analog input (0.2 V–2.5 V)
GPIO
GPIO1 4 I/O General-purpose discrete I/O
GPIO2 5 I/O General-purpose discrete I/O
GPIO3 6 I/O General-purpose discrete I/O
GPIO4 7 I/O General-purpose discrete I/O
GPIO13 18 I/O General-purpose discrete I/O
GPIO14 21 I/O General-purpose discrete I/O
GPIO15 24 I/O General-purpose discrete I/O
GPIO16 25 I/O General-purpose discrete I/O
GPIO17 26 I/O General-purpose discrete I/O
PWM OUTPUTS
FPWM1/GPIO5 10 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM2/GPIO6 11 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM3/GPIO7 12 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM4/GPIO8 13 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM5/GPIO9 14 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM6/GPIO10 15 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM7/GPIO11 16 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM8/GPIO12 17 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
PWM1/GPI1 22 I/PWM PWM (0.93 Hz to 7.8125 MHz) or GPI
PWM2/GPI2 23 I/PWM PWM (0.93 Hz to 7.8125 MHz) or GPI
PMBus COMM INTERFACE
PMBus_CLK 8 I/O PMBus clock (must have pullup to 3.3 V)
PMBus_DATA 9 I/O PMBus data (must have pullup to 3.3 V)
PMBus_ALERT 19 O PMBus alert, active-low, open-drain output (must have pullup to 3.3 V)
PMBus_CNTRL 20 I PMBus control
PMBus_ADDR0 44 I PMBus analog address input. Least-significant address bit
PMBus_ADDR1 43 I PMBus analog address input. Most-significant address bit
JTAG
TCK/GPIO18 27 I/O Test clock or GPIO
TDO/GPIO19 28 I/O Test data out or GPIO
TDI/GPIO20 29 I/O Test data in (tie to Vdd with 10-kΩ resistor) or GPIO
TMS/GPIO21 30 I/O Test mode select (tie to Vdd with 10-kΩ resistor) or GPIO
TRST 31 I Test reset – tie to ground with 10-kΩ resistor
INPUT POWER AND GROUNDS
RESET 3 — Active-low device reset input. Hold low for at least 2 μs to reset the device.
V33A 34 — Analog 3.3-V supply. Refer to the Section 10.1 section.
V33D 33 — Digital core 3.3-V supply. Refer to the Section 10.1 section.
BPCap 35 — 1.8-V bypass capacitor. Refer to the Section 10.1 section.
AVSS1 36 — Analog ground
AVSS2 47 — Analog ground
DVSS 32 — Digital ground
Thermal pad — QFN ground pad. Tie to ground plane.
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