ZHCSC55A January 2014 – March 2014 UCD9244-EP
PRODUCTION DATA.
- 1 特性
- 2 应用范围
- 3 说明
- 4 修订历史记录
- 5 说明（继续）
- 6 Terminal Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 Handling Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 Electrical Characteristics (Continued)
- 7.7 ADC Monitoring Intervals And Response Times
- 7.8 Hardware Fault Detection Latency
- 7.9 PMBus/SMBus/I2C
- 7.10 I2C/SMBus/PMBus Timing Requirements
- 7.11 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 PMBus Interface
- 8.3.2 Resistor Programmed PMBus Address Decode
- 8.3.3 VID Interface
- 8.3.4 Jtag Interface
- 8.3.5 Bias Supply Generator (Shunt Regulator Controller)
- 8.3.6 Power-On Reset
- 8.3.7 External Reset
- 8.3.8 ON_OFF_CONFIG
- 8.3.9 Output Voltage Adjustment
- 8.3.10 Calibration
- 8.3.11 Analog Front End (AFE)
- 8.3.12 Voltage Sense Filtering
- 8.3.13 DPWM Engine
- 8.3.14 Rail/Power Stage Configuration
- 8.3.15 DPWM Phase Synchronization
- 8.3.16 Output Current Measurement
- 8.3.17 Current Sense Input Filtering
- 8.3.18 Over-Current Detection
- 8.3.19 Input Voltage Monitoring
- 8.3.20 Input UV Lockout
- 8.3.21 Temperature Monitoring
- 8.3.22 Auxiliary ADC Input Monitoring
- 8.3.23 Soft Start, Soft Stop Ramp Sequence
- 8.3.24 Non-Volatile Memory Error Correction Coding
- 8.3.25 Data Logging
- 8.4 Device Functional Modes
- 9 Applications and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
11 Layout
11.1 Layout Guidelines
The UCD9244 device has separate analog and digital ground terminals, and separate analog, digital, and I/O power terminals. Tying the analog and digital ground together to a ground plane under the controller has been shown to produce good results. The V33A terminal requires very good decoupling. If desired, this terminal can be separated from the V33D and V33IO terminals with a ferrite bead; in most cases, this bead is not necessary.
11.2 Layout Example
Figure 19. Recommended Decoupling Capacitor LayoutRefer to design guide SLUU490 for details.