ZHCSC55A January   2014  – March 2014 UCD9244-EP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明（继续）
  6. 6 Terminal Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Handling Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics (Continued)
    7. 7.7  ADC Monitoring Intervals And Response Times
    8. 7.8  Hardware Fault Detection Latency
    9. 7.9  PMBus/SMBus/I2C
    10. 7.10 I2C/SMBus/PMBus Timing Requirements
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  PMBus Interface
      2. 8.3.2  Resistor Programmed PMBus Address Decode
      3. 8.3.3  VID Interface
      4. 8.3.4  Jtag Interface
      5. 8.3.5  Bias Supply Generator (Shunt Regulator Controller)
      6. 8.3.6  Power-On Reset
      7. 8.3.7  External Reset
      8. 8.3.8  ON_OFF_CONFIG
      9. 8.3.9  Output Voltage Adjustment
      10. 8.3.10 Calibration
      11. 8.3.11 Analog Front End (AFE)
      12. 8.3.12 Voltage Sense Filtering
      13. 8.3.13 DPWM Engine
      14. 8.3.14 Rail/Power Stage Configuration
      15. 8.3.15 DPWM Phase Synchronization
      16. 8.3.16 Output Current Measurement
      17. 8.3.17 Current Sense Input Filtering
      18. 8.3.18 Over-Current Detection
      19. 8.3.19 Input Voltage Monitoring
      20. 8.3.20 Input UV Lockout
      21. 8.3.21 Temperature Monitoring
      22. 8.3.22 Auxiliary ADC Input Monitoring
      23. 8.3.23 Soft Start, Soft Stop Ramp Sequence
      24. 8.3.24 Non-Volatile Memory Error Correction Coding
      25. 8.3.25 Data Logging
    4. 8.4 Device Functional Modes
      1. 8.4.1 4-Bit VID Mode
      2. 8.4.2 6-Bit VID Mode
      3. 8.4.3 8-Bit VID Mode
      4. 8.4.4 Current Foldback Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Automatic System Identification (Auto-ID)
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Digital Compensator
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Terminal Configuration and Functions

RGC Package
QFN-64
(Top View)
po_slvsc86.gif
1. In case of conflict between and the table shall take precedence
2. Preliminary versions of this data sheet prior to June 14, 2010 had a different definition for terminals 17, 18, and 21. Board designs made with that earlier pinout should be updated.

Terminal Functions

TERMINAL NUMBER TERMINAL LABEL TERMINAL DESCRIPTION
1 CS4A Power stage 4A current sense input and input to analog comparator 4
2 CS3A Power stage 3A current sense input and input to analog comparator 3
3 CS2A Power stage 2A current sense input and input to analog comparator 2
4 VinMon Input Voltage monitor
5 Temp1/AuxADC1 Temperature sense input for Rail 1, or Auxiliary ADC input 1
6 Temp2/AuxADC2 Temperature sense input for Rail 2, or Auxiliary ADC input 2
7 V33DIO1 Digital Input / Output 3.3V supply
8 Dgnd1 Digital ground
9 nRESET Active low device reset input. Pull up to 3.3V with a 10kΩ resistor
10 JTAG_RCK JTAG Return Clock
11 FLT1A Fault indicator for stage 1A
12 VID1S VID Select terminal for Rail 1
13 FLT2A Fault indicator for stage 2A
14 VID2S VID Select terminal for Rail 2
15 PMBus_Clk PMBus Clock. Pull up to 3.3V with a 2kΩ resistor
16 PMBus_Data PMBus Data. Pull up to 3.3V with a 2kΩ resistor
17 DPWM1A Digital Pulse Width Modulator output 1A
18 VID1C VID input terminal for Rail 1 - most significant bit
19 DPWM2A Digital Pulse Width Modulator output 2A
20 VID2A VID input terminal for Rail 2 - least significant bit
21 DPWM3A Digital Pulse Width Modulator output 3A
22 VID2B VID input terminal for Rail 2
23 DPWM4A Digital Pulse Width Modulator output 4A
24 Power_Good Power Good Indication
25 FLT3A Fault indicator for stage 3A
26 Dgnd2 Digital Ground
27 PMBus_Alert PMBus Alert. Pull up to 3.3V with a 2kΩ resistor
28 PMBus_Cntrl PMBus Control. Pull up to 3.3V with a 2kΩ resistor
29 VID2C VID input terminal for Rail 2 - most significant bit
30 VID3A VID input terminal for Rail 3 - least significant bit
31 VID3B VID input terminal for Rail 3
32 VID3C VID input terminal for Rail 3 - most significant bit
33 VID3S VID Select terminal for Rail 3
34 FLT4A Fault indicator for stage 4A
35 VID4S VID Select terminal for Rail 4
36 VID4A/JTAG_TCK Mux'ed terminal - VID input terminal for Rail 4 (LSB), JTAG Test Clock
37 VID4B/JTAG_TDO Mux'ed terminal - VID input terminal for Rail 4, JTAG Test Data Output
38 SyncIn/JTAG_TDI Mux'ed terminal - SyncIn, JTAG Test Data In. Tie to V33D with 10kΩ resistor
39 VID4C/JTAG_TMS Mux'ed terminal - VID input for rail 4 (MSB); JTAG Test mode select. Tie to V33D with a 10kΩ resistor
40 JTAG_nTRST JTAG Test Reset - Tie to ground with a 10kohm resistor
41 VID1A VID input terminal for Rail 1 - least significant bit
42 VID1B VID input terminal for Rail 1
43 Dgnd3 Digital Ground
44 V33DIO2 Digital Input / Output 3.3V supply
45 V33D Digital core 3.3V supply
46 V33A Analog 3.3V supply
47 BPCap 1.8V Bypass Capacitor -- tie 0.1µF cap to analog ground
48 Agnd2 Analog ground
49 Agnd1 Analog ground
50 EAp1 Error analog, differential voltage, Positive channel 1 input
51 EAn1 Error analog, differential voltage, Negative channel 1 input
52 EAp2 Error analog, differential voltage, Positive channel 2 input
53 EAn2 Error analog, differential voltage, Negative channel 2 input
54 EAp3 Error analog, differential voltage, Positive channel 3 input
55 EAn3 Error analog, differential voltage, Negative channel 3 input
56 EAp4 Error analog, differential voltage, Positive channel 4 input
57 EAn4 Error analog, differential voltage, Negative channel 4 input
58 V33FB Connection to the base of 3.3V linear regulator transistor (no connect if unused)
59 CS1A Power stage 1A current sense input and input to analog comparator 1
60 Addr1 PMBus Address sense. Channel 1.
61 Addr0 PMBus Address sense. Channel 0.
62 Temp3/AuxADC3 Temperature sense input for Rail 3, or Auxiliary ADC input 3
63 Temp4/AuxADC4 Temperature sense input for Rail 4, or Auxiliary ADC input 4
64 Agnd3 Analog ground
PowerPad It is recommended that this pad be connected to analog ground
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