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ZHCSC42J July 2013 – October 2014 WL1801MOD , WL1805MOD , WL1831MOD , WL1835MOD

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MOC|100

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5 Specifications

5.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

PARAMETER	VALUE	UNIT
VBAT	4.8⁽²⁾	V
VIO	–0.5 to 2.1	V
Input voltage to analog pins	–0.5 to 2.1	V
Input voltage limits (CLK_IN)	–0.5 to VDD_IO	V
Input voltage to all other pins	–0.5 to (VDD_IO + 0.5 V)	V
Operating ambient temperature range	–20 to +70⁽³⁾	°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) 4.8 V cumulative to 2.33 years, including charging dips and peaks

(3) Operating free-air temperature range at which the device can operate reliably for 15K cumulative active TX power-on hours (assuming a maximum junction temperature of (T_j) of 125°C). Section 5.3, Power-On Hours (POH), describes the correlation between T_j and PoH. In the WL18xx system, a control mechanism automatically ensures T_j < 125°C. Whenever T_j approaches the threshold, this mechanism controls the transmitter patterns.

5.2 Handling Ratings

		MIN	MAX	UNIT
T_stg	Storage temperature range	–40	+85	°C
ESD stress voltage⁽¹⁾	Human body model (HBM)⁽²⁾	–1000	+1000	V
ESD stress voltage⁽¹⁾	Charged device model (CDM)⁽³⁾	–250	+250	V

(1) ESD measures device sensitivity and immunity to damage caused by electrostatic discharges into the device.

(2) The level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500-V HBM is possible, if necessary precautions are taken. Pins listed as 1000 V can actually have higher performance.

(3) The level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 250-V CDM is possible, if necessary precautions are taken. Pins listed as 250 V can actually have higher performance.

5.3 Power-On Hours (POH)

OPERATING JUNCTION TEMPERATURE (°C)	POH
125	15,000
120	20,000
115	27,000
110	37,000
105	50,000

5.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
VBAT⁽²⁾	DC supply range for all modes		2.9	4.8	V
	1.8-V I/O ring power supply voltage		1.62	1.95	V
V_IH	I/O high-level input voltage		0.65 x VDD_IO	VDD_IO	V
V_IL	I/O low-level input voltage		0	0.35 × VDD_IO	V
VIH_EN	Enable inputs high-level input voltage		1.365	VDD_IO	V
VIL_EN	Enable inputs low-level input voltage		0	0.4	V
V_OH	High-level output voltage	@ 4 mA	VDD_IO –0.45	VDD_IO	V
V_OL	Low-level output voltage	@ 4 mA	0	0.45	V
T_r,T_f	Input transitions time T_r,T_f from 10% to 90% (digital I/O)⁽¹⁾		1	10	ns
T_r	Output rise time from 10% to 90% (digital pins)⁽¹⁾	C_L < 25 pF		5.3	ns
T_f	Output fall time from 10% to 90% (digital pins)⁽¹⁾	C_L < 25 pF		4.9	ns
	Ambient operating temperature		–20	70	ºC
Maximum power dissipation	WLAN operation			2.8	W
Maximum power dissipation	Bluetooth operation			0.2	W

(1) Applies to all digital lines except SDIO, UART, I2C, PCM and slow clock lines

(2) 4.8 V is applicable only for 2.3 years (30% of the time). Otherwise, maximum VBAT must not exceed 4.3 V.

5.5 External Digital Slow Clock Requirements

The supported digital slow clock is 32.768 kHz digital (square wave). All core functions share a single input.

PARAMETER	CONDITION	SYMBOL	MIN	TYP	MAX	UNIT
Input slow clock frequency				32768		Hz
Input slow clock accuracy (Initial + temp + aging)	WLAN, Bluetooth				±250	ppm
Input transition time T_r,T_f (10% to 90%)		T_r,T_f			200	ns
Frequency input duty cycle			15	50	85	%
Input voltage limits	Square wave, DC-coupled	Vih	0.65 x VDD_IO		VDD_IO	V_peak
Input voltage limits	Square wave, DC-coupled	Vil	0		0.35 x VDD_IO	V_peak
Input impedance			1			MΩ
Input capacitance					5	pF

5.6 Thermal Characteristics

AIR FLOW
NAME	DESCRIPTION	FCBGA (°C/W)⁽¹⁾
θ_JC	Junction to case	12.7
θ_JB	Junction to board	13.6
θ_JA	Junction to free air⁽²⁾	20.5
φ_JB	Junction to board	8.7

(1) °C/W = degrees Celsius per watt

(2) According to the JEDEC EIA/JESD 51 document

5.7 WLAN Performance

All RF and performance numbers are aligned to the module pin.

5.7.1 WLAN 2.4-GHz Receiver Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER	CONDITION	MIN	TYP	MAX	UNIT
Operation frequency range	2400 to 2480	2400		2480	MHz
Sensitivity: 20-MHz bandwidth. At < 10% PER limit	1 Mbps DSSS		–96.3		dBm
	2 Mbps DSSS		–93.2
	5.5 Mbps CCK		–90.6
	11 Mbps CCK		–87.9
	6 Mbps OFDM		–92.0
	9 Mbps OFDM		–90.4
	12 Mbps OFDM		–89.5
	18 Mbps OFDM		–87.2
	24 Mbps OFDM		–84.1
	36 Mbps OFDM		–80.7
	48 Mbps OFDM		–76.5
	54 Mbps OFDM		–74.9
	MCS0 MM 4K		–90.4
	MCS1 MM 4K		–87.6
	MCS2 MM 4K		–85.9
	MCS3 MM 4K		–82.8
	MCS4 MM 4K		–79.4
	MCS5 MM 4K		–75.2
	MCS6 MM 4K		–73.5
	MCS7 MM 4K		–72.4
	MCS0 MM 4K 40 MHz		–86.7
	MCS7 MM 4K 40 MHz		–67.0
	MCS0 MM 4K MRC		–92.7
	MCS7 MM 4K MRC		–75.2
	MCS13 MM 4K		–73.7
	MCS14 MM 4K		–72.3
	MCS15 MM 4K		–71.0
Max Input Level At < 10% PER limit	OFDM (11g/n)	–19	–9		dBm
Max Input Level At < 10% PER limit	DSSS	–4	–0		dBm
Adjacent channel rejection: Sensitivity level +3 dB for OFDM; Sensitivity level +6 dB for 11b	2 Mbps DSSS	42.7			dB
	11 Mbps CCK	37.9			dB
	54 Mbps OFDM	2.0			dB

5.7.2 WLAN 2.4-GHz Transmitter Power

over operating free-air temperature range (unless otherwise noted)

PARAMETER	CONDITION	MIN	TYP	MAX	UNIT
	RF_IO2_BG_WL pin 2.4-GHz SISO
Output Power: Maximum RMS output power measured at 1 dB from IEEE spectral mask or EVM⁽¹⁾	1 Mbps DSSS		17.3		dBm
	2 Mbps DSSS		17.3
	5.5 Mbps CCK		17.3
	11 Mbps CCK		17.3
	6 Mbps OFDM		17.1
	9 Mbps OFDM		17.1
	12 Mbps OFDM		17.1
	18 Mbps OFDM		17.1
	24 Mbps OFDM		16.2
	36 Mbps OFDM		15.3
	48 Mbps OFDM		14.6
	54 Mbps OFDM		13.8
	MCS0 MM		16.1
	MCS1 MM		16.1
	MCS2 MM		16.1
	MCS3 MM		16.1
	MCS4 MM		15.3
	MCS5 MM		14.6
	MCS6 MM		13.8
	MCS7 MM⁽²⁾		12.6
	MCS0 MM 40 MHz		14.8
	MCS7 MM 40 MHz		11.3
	2G4_ANT2_W + 2G4_ANT1_WB 2.4-GHz MIMO
	MCS12 (WL18x5)		18.5		dBm
	MCS13 (WL18x5)		17.4
	MCS14 (WL18x5)		14.5
	MCS15 (WL18x5)		13.4
	2G4_ANT2_W + 2G4_ANT1_WB Pins
Operation frequency range		2412		2484	MHz
Return loss			–10.0		dB
Reference input impedance			50.0		Ω

(1) Regulatory constraints limit TI module output power to the following:

Channels 1, 11, 13 @ OFDM legacy and HT 20-MHz rates: 14 dBm
Channels 1, 11, 13 @ HT 40-MHz lower primary rates: 12 dBm
Channel 7 @ HT 40-MHz lower primary rates: 12 dBm
Channel 5 @ HT 40-MHz upper primary rates: 12 dBm

(2) To ensure compliance with the EVM conditions specified in the PHY chapter of IEEE Std 802.11™ – 2012:

MCS7 20 MHz channel 12 output power is 2 dB lower than the typical value.
MCS7 20 MHz channel 8 output power is 1 dB lower than the typical value.

5.7.3 WLAN Currents

	SPECIFICATION ITEMS	TYP (AVG) – 25°C	UNITS
Receiver	Low-power mode (LPM) 2.4-GHz RX SISO20 single chain	49	mA
	2.4 GHz RX search SISO20	54	mA
	2.4-GHz RX search MIMO20	74	mA
	2.4-GHz RX search SISO40	59	mA
	2.4-GHz RX 20 M SISO 11 CCK	56	mA
	2.4-GHz RX 20 M SISO 6 OFDM	61	mA
	2.4-GHz RX 20 M SISO MCS7	65	mA
	2.4-GHz RX 20 M MRC 1 DSSS	74	mA
	2.4-GHz RX 20 M MRC 6 OFDM	81	mA
	2.4-GHz RX 20 M MRC 54 OFDM	85	mA
	2.4-GHz RX 40 MHz MCS7	77	mA
Transmitter	2.4-GHz TX 20 M SISO 6 OFDM 15.4 dBm	285	mA
	2.4-GHz TX 20 M SISO 11 CCK 15.4 dBm	273	mA
	2.4-GHz TX 20 M SISO 54 OFDM 12.7 dBm	247	mA
	2.4-GHz TX 20 M SISO MCS7 11.2 dBm	238	mA
	2.4-GHz TX 20 M MIMO MCS15 11.2 dBm	420	mA
	2.4-GHz TX 40 M SISO MCS7 8.2 dBm	243	mA

5.8 Bluetooth Performance

All RF and performance numbers are aligned to the module pin.

5.8.1 Bluetooth BR, EDR Receiver Characteristics—In-Band Signals

over operating free-air temperature range (unless otherwise noted)

PARAMETER	CONDITION		MIN	TYP	MAX	UNIT
Bluetooth BR, EDR operation frequency range			2402		2480	MHz
Bluetooth BR, EDR channel spacing				1		MHz
Bluetooth BR, EDR input impedance				50		Ω
Bluetooth BR, EDR sensitivity⁽¹⁾ dirty TX on	BR, BER = 0.1%			–92.2		dBm
	EDR2, BER = 0.01%			–91.7		dBm
	EDR3, BER = 0.01%			–84.7		dBm
Bluetooth EDR BER floor at sensitivity + 10 dB Dirty TX off (for 1,600,000 bits)	EDR2		1e-6
	EDR3		1e-6
Bluetooth BR, EDR maximum usable input power	BR, BER = 0.1%		–5.0			dBm
	EDR2, BER = 0.1%		–15.0			dBm
	EDR3, BER = 0.1%		–15.0			dBm
Bluetooth BR intermodulation	Level of interferers for n = 3, 4, and 5		–36.0	–30.0		dBm
Bluetooth BR, EDR C/I performance Numbers show wanted signal-to-interfering-signal ratio. Smaller numbers indicate better C/I performances (Image frequency = –1 MHz)	BR, co-channel				10	dB
	EDR, co-channel	EDR2			12	dB
	EDR, co-channel	EDR3			20	dB
	BR, adjacent ±1 MHz				–3.0	dB
	EDR, adjacent ±1 MHz, (image)	EDR2			–3.0	dB
	EDR, adjacent ±1 MHz, (image)	EDR3			2.0	dB
	BR, adjacent +2 MHz				–33.0	dB
	EDR, adjacent +2 MHz	EDR2			–33.0	dB
	EDR, adjacent +2 MHz	EDR3			–28.0	dB
	BR, adjacent –2 MHz				–20.0	dB
	EDR, adjacent –2 MHz	EDR2			–20.0	dB
	EDR, adjacent –2 MHz	EDR3			–13.0	dB
	BR, adjacent ≥Ι±3Ι MHz				–42.0	dB
	EDR, adjacent ≥Ι±3Ι MHz	EDR2			–42.0	dB
	EDR, adjacent ≥Ι±3Ι MHz	EDR3			–36.0	dB
Bluetooth BR, EDR RF return loss				–10.0		dB

(1) Sensitivity degradation up to –3 dB may occur due to fast clock harmonics with dirty TX on.

5.8.2 Bluetooth Transmitter, BR

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TYP	UNIT
BR RF output power⁽¹⁾	VBAT ≥ 3 V	12.7	dBm
BR RF output power⁽¹⁾	VBAT < 3 V	7.2	dBm
BR gain control range		30.0	dB
BR power control step		5.0	dB
BR adjacent channel power \|M-N\| = 2		–43.0	dBm
BR adjacent channel power \|M-N\| > 2		–48.0	dBm

(1) Values reflect maximum power. Reduced power is available using a vendor-specific (VS) command.

5.8.3 Bluetooth Transmitter, EDR

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TYP	UNIT
EDR output power⁽¹⁾	VBAT ≥ 3 V	7.2	dBm
EDR output power⁽¹⁾	VBAT < 3 V	5.2
EDR relative power			dB
EDR gain control range		30	dB
EDR power control step		5	dB
EDR adjacent channel power \|M-N\| = 1		–36	dBc
EDR adjacent channel power \|M-N\| = 2		–30	dBm
EDR adjacent channel power \|M-N\| > 2		–42	dBm

(1) Values reflect default maximum power. Max power can be changed using a VS command.

5.8.4 Bluetooth Modulation, BR

over operating free-air temperature range (unless otherwise noted)

CHARACTERISTICS	CONDITION⁽¹⁾		MIN	TYP	MAX	UNIT
BR –20 dB bandwidth				925	995	kHz
BR modulation characteristics	∆f1avg	Mod data = 4 1s, 4 0s: 111100001111...	145	160	170	kHz
	∆f2max ≥ limit for at least 99.9% of all Δf2max	Mod data = 1010101...	120	130		kHz
	∆f2avg, ∆f1avg		85	88		%
BR carrier frequency drift	One slot packet		–25		25	kHz
	Three and five slot packet		–35		35	kHz
BR drift rate	lfk+5 – fkl , k = 0 …. max				15	kHz/50 µs
BR initial carrier frequency tolerance⁽²⁾	f0–fTX		±75		±75	kHz

(1) Performance values reflect maximum power.

(2) Numbers include XTAL frequency drift over temperature and aging.

5.8.5 Bluetooth Modulation, EDR

over operating free-air temperature range (unless otherwise noted)

PARAMETER⁽¹⁾	CONDITION	MIN	TYP	MAX	UNIT
EDR carrier frequency stability		–5		5	kHz
EDR initial carrier frequency tolerance⁽²⁾		±75		±75	kHz
EDR RMS DEVM	EDR2		4	15	%
	EDR3		4	10	%
EDR 99% DEVM	EDR2			30	%
	EDR3			20	%
EDR peak DEVM	EDR2		9	25	%
	EDR3		9	18	%

(1) Performance values reflect maximum power.

(2) Numbers include XTAL frequency drift over temperature and aging.

5.9 Bluetooth LE Performance

All RF and performance numbers are aligned to the module pin.

5.9.1 Bluetooth LE Receiver Characteristics – In-Band Signals

over operating free-air temperature range (unless otherwise noted)

PARAMETER	CONDITION⁽²⁾	MIN	TYP	MAX	UNIT
Bluetooth LE operation frequency range		2402		2480	MHz
Bluetooth LE channel spacing			2		MHz
Bluetooth LE input impedance			50		Ω
Bluetooth LE sensitivity⁽¹⁾ Dirty TX on			–92.2		dBm
Bluetooth LE maximum usable input power		–5			dBm
Bluetooth LE intermodulation characteristics	Level of interferers. For n = 3, 4, 5	–36	–30		dBm
Bluetooth LE C/I performance. Note: Numbers show wanted signal-to-interfering-signal ratio. Smaller numbers indicate better C/I performance.	LE, co-channel			12	dB
	LE, adjacent ±1 MHz			0
	LE, adjacent +2 MHz			–38
	LE, adjacent –2 MHz			–15
Image = –1 MHz	LE, adjacent ≥ \|±3\|MHz			–40

(1) Sensitivity degradation of up to –3 dB can occur due to fast clock harmonics.

(2) BER of 0.1% corresponds to PER of 30.8% for a minimum of 1500 transmitted packets, according to the Bluetooth LE test specification.

5.9.2 Bluetooth LE Transmitter Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TYP	UNIT
Bluetooth LE RF output power⁽¹⁾	VBAT ≥ 3 V	10.0	dBm
Bluetooth LE RF output power⁽¹⁾	VBAT < 3 V	7.2	dBm
Bluetooth LE adjacent channel power \|M-N\| = 2		–51.0	dBm
Bluetooth LE adjacent channel power \|M-N\| > 2		–54.0	dBm

(1) To reduce the maximum BLE power, use a VS command. The optional extra margin is offered to compensate for design losses, such as trace and filter losses, and to achieve the maximum allowed output power at system level.

5.9.3 Bluetooth LE Modulation Characteristics

over operating free-air temperature range (unless otherwise noted)

CHARACTERISTICS	CONDITION⁽¹⁾		MIN	TYP	MAX	UNIT
Bluetooth LE modulation characteristics	∆f1avg	Mod data = 4 1s, 4 0s: 111100001111...	240	250	260	kHz
	∆f2max ≥ limit for at least 99.9% of all Δf2max	Mod data = 1010101...	195	215		kHz
	∆f2avg, ∆f1avg		85	90		%
Bluetooth LE carrier frequency drift	lf0 – fnl , n = 2,3 …. K		–25		25	kHz
Bluetooth LE drift rate	lf1 – f0l and lfn – fn-5l ,n = 6,7…. K				15	kHz/50 µs
LE initial carrier frequency tolerance⁽²⁾	fn – fTX		±75		±75	kHz

(1) Performance values reflect maximum power.

(2) Numbers include XTAL frequency drift over temperature and aging.

5.10 Bluetooth-BLE Dynamic Currents

Current is measured at output power as follows:

BR at 12.7 dBm
EDR at 7.2 dBm

USE CASE⁽¹⁾⁽²⁾	TYP	UNIT
BR voice HV3 + sniff	11.6	mA
EDR voice 2-EV3 no retransmission + sniff	5.9	mA
Sniff 1 attempt 1.28 s	178.0	µA
EDR A2DP EDR2 (master). SBC high quality – 345 Kbs	10.4	mA
EDR A2DP EDR2 (master). MP3 high quality – 192 Kbs	7.5	mA
Full throughput ACL RX: RX-2DH5⁽³⁾⁽⁴⁾	18.0	mA
Full throughput BR ACL TX: TX-DH5⁽⁴⁾	50.0	mA
Full throughput EDR ACL TX: TX-2DH5⁽⁴⁾	33.0	mA
Page scan or inquiry scan (scan interval is 1.28 s or 11.25 ms, respectively)	253.0	µA
Page scan and inquiry scan (scan interval is 1.28 s and 2.56 s, respectively)	332.0	µA

(1) The role of Bluetooth in all scenarios except A2DP is slave.

(2) CL1P5 PA is connected to VBAT, 3.7 V.

(3) ACL RX has the same current in all modulations.

(4) Full throughput assumes data transfer in one direction.

5.11 Bluetooth LE Currents

All current measured at output power of 7.2 dBm

USE CASE⁽¹⁾	TYP	UNIT
Advertising, not connectable⁽²⁾	131	µA
Advertising, discoverable⁽²⁾	143	µA
Scanning⁽³⁾	266	µA
Connected, master role, 1.28-s connect interval⁽⁴⁾	124	µA
Connected, slave role, 1.28-s connect interval ⁽⁴⁾	132	µA

(1) CL1p% PA is connected to VBAT, 3.7 V.

(2) Advertising in all three channels, 1.28-s advertising interval, 15 bytes advertise data

(3) Listening to a single frequency per window, 1.28-s scan interval, 11.25-ms scan window

(4) Zero slave connection latency, empty TX and RX LL packets

5.12 Timing and Switching Characteristics

5.12.1 Power Management

5.12.1.1 Block Diagram – Internal DC2DCs

The device incorporates three internal DC2DCs (switched-mode power supplies) to provide efficient internal supplies, derived from V_BAT.

Figure 5-1 Internal DC2DCs

5.12.2 Power-Up and Shut-Down States

The correct power-up and shut-down sequences must be followed to avoid damage to the device.

While V_BAT or V_IO or both are deasserted, no signals should be driven to the device. The only exception is the slow clock that is a fail-safe I/O.

While V_BAT, V_IO, and slow clock are fed to the device, but WL_EN is deasserted (low), the device is in SHUTDOWN state. In SHUTDOWN state all functional blocks, internal DC2DCs, clocks, and LDOs are disabled.

To perform the correct power-up sequence, assert (high) WL_EN. The internal DC2DCs, LDOs, and clock start to ramp and stabilize. Stable slow clock, V_IO, and V_BAT are prerequisites to the assertion of one of the enable signals.

To perform the correct shut-down sequence, deassert (low) WL_EN while all the supplies to the device (V_BAT, V_IO, and slow clock) are still stable and available. The supplies to the chip (V_BAT and V_IO) can be deasserted only after both enable signals are deasserted (low).

Figure 5-2 shows the general power scheme for the module, including the powerdown sequence.

NOTE: 1. Either VBAT or VIO can come up first.

2. VBAT and VIO supplies and slow clock (SCLK), must be stable prior to EN being asserted and at all times

when the EN is active.

3. At least 60 µs is required between two successive device enables. The device is assumed to be in

shutdown state during that period, meaning all enables to the device are LOW for that minimum duration.

4. EN must be deasserted at least 10 µs before VBAT or VIO supply can be lowered. (Order of supply turn off

after EN shutdown is immaterial)

5. SCLK - Fail safe I/O

Figure 5-2 Power-Up System

5.12.3 Chip Top-level Power-Up Sequence

Figure 5-3 Chip Top-Level Power-Up Sequence

5.12.4 WLAN Power-Up Sequence

Figure 5-4 WLAN Power-Up Sequence

5.12.5 Bluetooth-BLE Power-Up Sequence

Figure 5-5 shows the Bluetooth-BLE power-up sequence.

Figure 5-5 Bluetooth/BLE Power-Up Sequence

5.12.6 WLAN SDIO Transport Layer

The SDIO is the host interface for WLAN. The interface between the host and the WL18xx module uses an SDIO interface and supports a maximum clock rate of 50 MHz.

The device SDIO also supports the following features of the SDIO V3 specification:

4-bit data bus
Synchronous and asynchronous in-band interrupt
Default and high-speed (HS, 50 MHz) timing
Sleep and wake commands

5.12.6.1 SDIO Timing Specifications

Figure 5-6 and Figure 5-7 show the SDIO switching characteristics over recommended operating conditions and with the default rate for input and output.

Figure 5-6 SDIO Default Input Timing

Figure 5-7 SDIO Default Output Timing

Table 5-1 lists the SDIO default timing characteristics.

Table 5-1 SDIO Default Timing Characteristics⁽¹⁾

PARAMETER⁽²⁾		MIN	MAX	UNIT
f_clock	Clock frequency, CLK	0.0	26.0	MHz
DC	Low, high duty cycle	40.0	60.0	%
t_TLH	Rise time, CLK		10.0	ns
t_THL	Fall time, CLK		10.0	ns
t_ISU	Setup time, input valid before CLK ↑	3.0		ns
t_IH	Hold time, input valid after CLK ↑	2.0		ns
t_ODLY	Delay time, CLK ↓ to output valid	7.0	10.0	ns
C_l	Capacitive load on outputs		15.0	pF

(1) To change the data out clock edge from the falling edge (default) to the rising edge, set the configuration bit.

(2) Parameter values reflect maximum clock frequency.

5.12.6.2 SDIO Switching Characteristics – High Rate

Figure 5-8 and Figure 5-9 show the parameters for maximum clock frequency.

Figure 5-8 SDIO HS Input Timing

Figure 5-9 SDIO HS Output Timing

Table 5-2 lists the SDIO high-rate timing characteristics.

Table 5-2 SDIO HS Timing Characteristics

PARAMETER		MIN	MAX	UNIT
f_clock	Clock frequency, CLK	0.0	52.0	MHz
DC	Low, high duty cycle	40.0	60.0	%
t_TLH	Rise time, CLK		3.0	ns
t_THL	Fall time, CLK		3.0	ns
t_ISU	Setup time, input valid before CLK ↑	3.0		ns
t_IH	Hold time, input valid after CLK ↑	2.0		ns
t_ODLY	Delay time, CLK ↑ to output valid	7.0	10.0	ns
C_l	Capacitive load on outputs		10.0	pF

5.12.7 HCI UART Shared Transport Layers for All Functional Blocks (Except WLAN)

The device incorporates a UART module dedicated to the Bluetooth shared-transport, host controller interface (HCI) transport layer. The HCI interface transports commands, events, and ACL between the Bluetooth device and its host using HCI data packets acting as a shared transport for all functional blocks except WLAN.

WLAN	SHARED HCI FOR ALL FUNCTIONAL BLOCKS EXCEPT WLAN	BLUETOOTH VOICE-AUDIO
WLAN HS SDIO	Over UART	Bluetooth PCM

The HCI UART supports most baud rates (including all PC rates) for all fast-clock frequencies up to a maximum of 4 Mbps. After power up, the baud rate is set for 115.2 kbps, regardless of the fast-clock frequency. The baud rate can then be changed using a VS command. The device responds with a Command Complete Event (still at 115.2 kbps), after which the baud rate change occurs.

HCI hardware includes the following features:

Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions
Receiver-transmitter underflow detection
CTS, RTS hardware flow control
4 wire (H4)

Table 5-3 lists the UART default settings.

Table 5-3 UART Default Setting

PARAMETER	VALUE
Bit rate	115.2 kbps
Data length	8 bits
Stop bit	1
Parity	None

5.12.7.1 UART 4-Wire Interface – H4

The interface includes four signals:

Flow control between the host and the device is byte-wise by hardware.

When the UART RX buffer of the device passes the flow-control threshold, the buffer sets the UART_RTS signal high to stop transmission from the host. When the UART_CTS signal is set high, the device stops transmitting on the interface. If HCI_CTS is set high in the middle of transmitting a byte, the device finishes transmitting the byte and stops the transmission.

Figure 5-10 shows the UART timing.

Figure 5-10 UART Timing Diagram

Table 5-4 lists the UART timing characteristics.

Table 5-4 UART Timing Characteristics

PARAMETER	CONDITION	SYMBOL	MIN	TYP	MAX	UNIT
Baud rate			37.5		4364	Kbps
Baud rate accuracy per byte	Receive-transmit		–2.5		+1.5	%
Baud rate accuracy per bit	Receive-transmit		–12.5		+12.5	%
CTS low to TX_DATA on		t3	0.0	2.0		µs
CTS high to TX_DATA off	Hardware flow control	t4			1.0	Byte
CTS high pulse width		t6	1.0			Bit
RTS low to RX_DATA on		t1	0.0	2.0		µs
RTS high to RX_DATA off	Interrupt set to 1/4 FIFO	t2			16.0	Bytes

Figure 5-11 shows the UART data frame.

Figure 5-11 UART Data Frame

5.12.8 Bluetooth Codec-PCM (Audio) Timing Specifications

Figure 5-12 shows the Bluetooth codec-PCM (audio) timing diagram.

Figure 5-12 Bluetooth Codec-PCM (Audio) Master Timing Diagram

Table 5-5 lists the Bluetooth codec-PCM master timing characteristics.

Table 5-5 Bluetooth Codec-PCM Master Timing Characteristics

PARAMETER	SYMBOL	MIN	MAX	UNIT
Cycle time	T_clk	162.76 (6.144 MHz)	15625 (64 kHz)	ns
High or low pulse width	T_s	35% of T_clk min
AUD_IN setup time	t_is	10.6
AUD_IN hold time	t_ih	0
AUD_OUT propagation time	t_op	0	15
FSYNC_OUT propagation time	t_op	0	15
Capacitive loading on outputs	C_l		40	pF

Table 5-6 lists the Bluetooth codec-PCM slave timing characteristics.

Table 5-6 Bluetooth Codec-PCM Slave Timing Characteristics

PARAMETER	SYMBOL	MIN	MAX	UNIT
Cycle time	T_clk	81.38 (12.266 MHz)		ns
High or low pulse width	T_w	35% of T_clk min
AUD_IN setup time	t_is	5
AUD_IN hold time	t_ih	0
AUD_FSYNC setup time	t_is	5
AUD_FSYNC hold time	t_ih	0
AUD_OUT propagation time	t_op	0	19
Capacitive loading on outputs	C_l		40	pF

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5 Specifications

5.1 Absolute Maximum Ratings(1)

5.2 Handling Ratings

5.3 Power-On Hours (POH)

5.4 Recommended Operating Conditions

5.5 External Digital Slow Clock Requirements

5.6 Thermal Characteristics

5.7 WLAN Performance

5.7.1 WLAN 2.4-GHz Receiver Characteristics

5.7.2 WLAN 2.4-GHz Transmitter Power

5.7.3 WLAN Currents

5.8 Bluetooth Performance

5.8.1 Bluetooth BR, EDR Receiver Characteristics—In-Band Signals

5.8.2 Bluetooth Transmitter, BR

5.8.3 Bluetooth Transmitter, EDR

5.8.4 Bluetooth Modulation, BR

5.8.5 Bluetooth Modulation, EDR

5.9 Bluetooth LE Performance

5.9.1 Bluetooth LE Receiver Characteristics – In-Band Signals

5.9.2 Bluetooth LE Transmitter Characteristics

5.9.3 Bluetooth LE Modulation Characteristics

5.10 Bluetooth-BLE Dynamic Currents

5.11 Bluetooth LE Currents

5.12 Timing and Switching Characteristics

5.12.1 Power Management

5.12.1.1 Block Diagram – Internal DC2DCs

5.12.2 Power-Up and Shut-Down States

5.12.3 Chip Top-level Power-Up Sequence

5.12.4 WLAN Power-Up Sequence

5.12.5 Bluetooth-BLE Power-Up Sequence

5.12.6 WLAN SDIO Transport Layer

5.12.6.1 SDIO Timing Specifications

Table 5-1 SDIO Default Timing Characteristics(1)

5.12.6.2 SDIO Switching Characteristics – High Rate

Table 5-2 SDIO HS Timing Characteristics

5.12.7 HCI UART Shared Transport Layers for All Functional Blocks (Except WLAN)

Table 5-3 UART Default Setting

5.12.7.1 UART 4-Wire Interface – H4

Table 5-4 UART Timing Characteristics

5.12.8 Bluetooth Codec-PCM (Audio) Timing Specifications

Table 5-5 Bluetooth Codec-PCM Master Timing Characteristics

Table 5-6 Bluetooth Codec-PCM Slave Timing Characteristics

5.1 Absolute Maximum Ratings⁽¹⁾

Table 5-1 SDIO Default Timing Characteristics⁽¹⁾