In the event of a wire break or similar output fault, the current through the IS pin fails to satisfy the intended transfer function defined in Equation 1. The gate voltage VG falls as the XTR111 control loop attempts to correct for the discrepancy, eventually railing out. This condition is detected by the XTR111, causing the error flag to be asserted. Testing of the error flag functionality using the XTR111-2EVM suggests a typical delay of 650-700μs before EF goes low after a wire break event. As the load current (measured prior to the wire break) increases, this assertion delay decreases slightly, due to the lower initial VG voltage. The effective output capacitance, including both parasitic and intentional capacitance, acts to slow the fall of the output pin voltage and delays the assertion of the error flag. Furthermore, any parasitic capacitance on the EF pin forms an RC time constant with the external pullup resistance, increasing the fall time of the EF pin.