7.3.4 Power On/Off Glitch

When power is turned on or off, most analog amplifiers generate some glitching of the output because of internal circuit thresholds and capacitive charges. Characteristics of the supply voltage, as well as its rise and fall time, directly influence output glitches. Load resistance and capacitive load also affect the amplitude.

The output disable control (OD) cannot fully suppress glitches during power-on and power-off, but reduces the energy significantly. The glitch consists of a small amount of current and capacitive charge (voltage) that reacts with the resistive and capacitive load. The bias current of the IA inputs that are normally connected to the output also generate a voltage across the load.

Figure 38 indicates no glitches when transitioning between disable and enable. This measurement is made with a load resistance of 1 kΩ and tested in the circuit configuration of Figure 40.

Figure 38. Output Signal During Toggle of OD

When the power is off or with low supply, the output is diode clamped to the momentary supply voltage, but can float while output disabled within those limits unless terminated. Only an external switch (relays or opto-relays) can isolate the output under such conditions. Refer to Figure 39 for an illustration of this configuration. The same consideration applies if low impedance zero output is required, even during power off.

Figure 39. Example for Opto-Relay Output Isolation