10.3 VQFN Package and Heat Sinking

The XTR305 is available in a VQFN package. This leadless, near-chip-scale package maximizes board space and enhances thermal and electrical characteristics of the device through an exposed thermal pad.

Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but printed circuit board (PCB) layout greatly influences overall heat dissipation. The thermal resistance from junction-to-ambient (θ_JA) is specified for the packages with the exposed thermal pad soldered to a normalized PCB, as described in the technical brief PowerPAD™ Thermally-Enhanced Package. See also EIA/JEDEC Specifications JESD51-0 to 7, VQFN/SON PCB Attachment, and Quad Flatpack No-Lead Logic Packages. These documents are available for download at www.ti.com.

Component population, layout of traces, layers, and air flow strongly influence heat dissipation. Worst-case load conditions should be tested in the real environment to ensure proper thermal conditions. Minimize thermal stress for proper long-term operation with a junction temperature well below +125°C.

The exposed lead-frame die pad on the bottom of the package must be connected to the V− pin.