SBAA457 June   2021 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1

 

  1.   Trademarks
  2.   Note
  3. 1Introduction
  4. 2Controller Mode
    1. 2.1 Controller Mode Configuration Options
      1. 2.1.1 Auto Clock Configuration With PLL Enabled
        1. 2.1.1.1 Supported Sample-Rates
        2. 2.1.1.2 Example 12-MHz MCLK
      2. 2.1.2 Auto Clock Detect With PLL Disabled
        1. 2.1.2.1 Supported Sample-Rates
        2. 2.1.2.2 Example
  5. 3Edge Sync for I2S and LJF in Controller Mode
    1. 3.1 Compatibility With Non-zero Offset
    2. 3.2 I2S Compatibility With Zero Offset (I2S only)

1 Introduction

The PCM6xx0 device family includes the following high-performance, analog-to-digital converters (ADC):

  • PCM6020 is a two-channel ADC
  • PCM6x40: PCM6240 and PCM6340 are quad-channel ADCs
  • PCM6x60: PCM6260 and PCM6360 are six-channel ADCs
  • PCM6480 is a quad-channel ADC with a quad-channel digital pulse density-modulation (PDM) microphone input.

This family of devices features a flexible audio serial interface that allows the device to be configured as either a controller or target. This document describes the modes, input parameters, and register coefficients required to configure the PCM6xx0 devices as an audio bus controller.
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