米6体育平台手机版

SBAA457 June 2021 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1

Trademarks
Note
1Introduction
2Controller Mode
1. 2.1 Controller Mode Configuration Options
  1. 2.1.1 Auto Clock Configuration With PLL Enabled
    1. 2.1.1.1 Supported Sample-Rates
    2. 2.1.1.2 Example 12-MHz MCLK
  2. 2.1.2 Auto Clock Detect With PLL Disabled
    1. 2.1.2.1 Supported Sample-Rates
    2. 2.1.2.2 Example
3Edge Sync for I2S and LJF in Controller Mode
1. 3.1 Compatibility With Non-zero Offset
2. 3.2 I2S Compatibility With Zero Offset (I2S only)

2.1.2 Auto Clock Detect With PLL Disabled

For the lowest power consumption, it can be desirable to disable the PLL and derive all clocks directly from MCLK. To disable the PLL in auto configuration mode, set bit 5 (AUTO_MODE_PLL_DIS) in MST_CFG0 (page 0, register 0x13). The required inputs for this mode are found in Table 2-5.

Table 2-5 Required Input Parameters for Controller Mode Auto Clock Configuration With PLL Disabled

USER-PROVIDED PARAMETER	REGISTER
FS MODE	Page 0, MST_CFG0 Register 0x13, Bit 3
FS_RATE	Page 0, MST_CFG1 Register 0x14, Bits 7-4
FS_BCLK_RATIO	Page 0, MST_CFG1 Register 0x14, Bits 3-0
MCLK_FREQ_SEL_MODE	Page 0, CLK_SRC Register 0x16, Bit 6
MCLK_RATIO_SEL	Page 0, CLK_SRC Register 0x16, Bits 5-3
MCLK_FREQ_SEL	Page 0, MST_CFG0 Register 0x13, Bits 2-0