Real-world voltage references have a finite output impedance and bandwidth. These limitations can cause the output voltage of the voltage reference to droop when it is loaded by the transient currents from the ADC reference input pin. Figure 3-10 shows a typical circuit where the impact of the voltage reference limitations can be monitored. The best way to judge the reference settling error is to look at the Vref_err pin. This pin compares the steady state reference input to the transient reference input. The Vsettling_err pin also shows effects of reference droop as it is the total settling error from the sample and hold and reference.

Figure 3-10 Monitoring Voltage Reference Settling

Figure 3-11 shows the transient simulation results for the voltage reference input on ADS8860. Notice the reference input has transient behavior related to the current transients.

Figure 3-11 Reference Transient Simulation