Design Goals

Design Description

This design is intended to translate a small unipolar signal to a wide bipolar signal. A common application is to translate a 5-V DAC output to a ±12-V bipolar signal. The document provides equations needed to calculate component values for other voltage range requirements. Important error sources are covered using calculations and simulation.

Design Notes

1. The OPA206 op amp was selected for excellent DC and AC characteristics as well as built-in robustness features. This topology works well for many different op amp selections.
2. Select 0.1% 20 ppm/°C resistors for good gain, offset accuracy, and drift.
   A calibration at room temperature can be used to minimize the gain error at room temperature, but gain drift can only be reduced by minimizing the resistor drift ( choosing resistors with TC ≤ 20 ppm/°C).
3. Place decoupling capacitors close to the device power supplies. The OPAx206 data sheet provides layout suggestions, and this video on Decoupling Capacitors provides further details.

Specifications

Design Steps

1. Define the input and output conditions.
   For this example, V_inMin = 0 V, V_inMax = 5 V, V_outMin = –12 V, V_outMax = 12 V.
2. Select a reference voltage. Generate this voltage from a precision source such as a series or shunt voltage reference (for example REF5050). Typically, a power-supply voltage developed by a low dropout regulator does not have sufficient accuracy to act as a reference. V_ref = 5 V in this example.
3. Choose a large resistance for R_f. Typical practical values range from 50 kΩ to 1 MΩ. R_f = 100 kΩ in this example.
4. Calculate gain based on the input range and output range.
   $\mathrm{G}=\frac{{\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}\mathrm{M}\mathrm{a}\mathrm{x}}-{\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}\mathrm{M}\mathrm{i}\mathrm{n}}}{{\mathrm{V}}_{\mathrm{i}\mathrm{n}\mathrm{M}\mathrm{a}\mathrm{x}}-{\mathrm{V}}_{\mathrm{i}\mathrm{n}\mathrm{M}\mathrm{i}\mathrm{n}}}=\frac{12\mathrm{V}\mathrm{ }-\mathrm{ }(-12\mathrm{V})}{5\mathrm{V}\mathrm{ }-0\mathrm{V}}=4.8$
5. Calculate R_g based on R_f and signal gain.
   ${\mathrm{R}}_{\mathrm{g}}=\frac{{\mathrm{R}}_{\mathrm{f}}}{\left(\mathrm{G}-1\right)}=\frac{100\mathrm{k}\mathrm{\Omega }}{\left(4.8-1\right)}=26.31\mathrm{k}\mathrm{\Omega }\mathrm{ }\mathrm{ }\left(26.4\mathrm{k}\mathrm{\Omega }\mathrm{ }\mathrm{s}\mathrm{t}\mathrm{a}\mathrm{n}\mathrm{d}\mathrm{a}\mathrm{r}\mathrm{d}\mathrm{ }\mathrm{v}\mathrm{a}\mathrm{l}\mathrm{u}\mathrm{e}\right)$
6. Calculate the output of the voltage divider based on minimum signal. If this number is negative, use a different topology. Also, this number must be less than V_ref from step 2.
   ${\mathrm{ }\mathrm{V}}_{\mathrm{d}\mathrm{i}\mathrm{v}}=\frac{{\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}\mathrm{M}\mathrm{i}\mathrm{n}}-{(\mathrm{V}}_{\mathrm{i}\mathrm{n}\mathrm{M}\mathrm{i}\mathrm{n}}\times \mathrm{G})}{\left(-{\mathrm{R}}_{\mathrm{f}}/{\mathrm{R}}_{\mathrm{g}}\right)}=\frac{-12\mathrm{V}-(0\mathrm{V}\times 10)}{\left(-{\mathrm{R}}_{\mathrm{f}}/{\mathrm{R}}_{\mathrm{g}}\right)}=3.168\mathrm{V}$
7. Calculate R₁ and R₂ to achieve the desired divider output. The equations used for this calculation assume that (R₁ || R₂) = R_g/100, so that R_g >> (R₁ || R₂). The reason this is done is that the voltage divider has an impact on gain. The actual gain including the voltage divider is 3.781, whereas the ideal gain was 4.8. The following equations show the algebraic rearrangement of the voltage divider equation to a ratio of R₁/R₂. This ratio is defined as α and used throughout the calculation.
   $\left(\frac{{\mathrm{R}}_2}{{\mathrm{R}}_1+{\mathrm{R}}_2}\right){\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}={\mathrm{V}}_{\mathrm{d}\mathrm{i}\mathrm{v}}\mathrm{rearrange to}\frac{{\mathrm{R}}_1}{{\mathrm{R}}_2}=\frac{{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{{\mathrm{V}}_{\mathrm{d}\mathrm{i}\mathrm{v}}}-1\mathrm{ }$
   $\mathrm{\alpha }=\frac{{\mathrm{R}}_1}{{\mathrm{R}}_2}=\frac{{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{{\mathrm{V}}_{\mathrm{d}\mathrm{i}\mathrm{v}}}-1\mathrm{ }=0.583\mathrm{ }(\mathrm{d}\mathrm{e}\mathrm{f}\mathrm{i}\mathrm{n}\mathrm{e}\mathrm{ }\mathrm{\alpha }\mathrm{ }\mathrm{a}\mathrm{s}\mathrm{ }{\mathrm{R}}_1/{\mathrm{R}}_2,\mathrm{ }\mathrm{s}\mathrm{u}\mathrm{b}\mathrm{s}\mathrm{t}\mathrm{i}\mathrm{t}\mathrm{u}\mathrm{t}\mathrm{e}\mathrm{ }{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}\mathrm{ }\mathrm{a}\mathrm{n}\mathrm{d}\mathrm{ }{\mathrm{V}}_{\mathrm{d}\mathrm{i}\mathrm{v}})$
   ${\mathrm{R}}_1=\frac{{\mathrm{R}}_{\mathrm{g}}}{100}\left(\mathrm{\alpha }+1\right)=418\mathrm{\Omega }\mathrm{ }\left(417\mathrm{\Omega }\mathrm{ }\mathrm{s}\mathrm{t}\mathrm{a}\mathrm{n}\mathrm{d}\mathrm{a}\mathrm{r}\mathrm{d}\mathrm{ }\mathrm{v}\mathrm{a}\mathrm{l}\mathrm{u}\mathrm{e}\right)$
   ${\mathrm{R}}_2={\mathrm{R}}_1/\mathrm{\alpha }=714.9\mathrm{\Omega }\mathrm{ }\left(\mathrm{o}\mathrm{r}\mathrm{ }715\mathrm{\Omega }\mathrm{ }\mathrm{s}\mathrm{t}\mathrm{a}\mathrm{n}\mathrm{d}\mathrm{a}\mathrm{r}\mathrm{d}\mathrm{ }\mathrm{v}\mathrm{a}\mathrm{l}\mathrm{u}\mathrm{e}\right)$
   ${\mathrm{G}}_{\mathrm{l}\mathrm{o}\mathrm{a}\mathrm{d}\mathrm{e}\mathrm{d}}=\frac{{\mathrm{R}}_{\mathrm{f}}}{{\mathrm{R}}_{\mathrm{g}}+\left({\mathrm{R}}_1\right|\left|{\mathrm{R}}_2\right)}+1=4.75\mathrm{ }\left(\mathrm{i}\mathrm{d}\mathrm{e}\mathrm{a}\mathrm{l}\mathrm{ }\mathrm{g}\mathrm{a}\mathrm{i}\mathrm{n}\mathrm{ }\mathrm{w}\mathrm{a}\mathrm{s}\mathrm{ }4.8\right)$
8. As an option, a buffer can be placed between the voltage divider and R_g. Doing this improves the accuracy and also eliminates the requirement that R_g >> (R₁ || R₂). See accuracy difference in the DC Transfer Characteristics section. In this case, the value of R_f can be selected as a smaller value which improves noise. Also, the divider resistors are independent from the feedback, so any values can be used for R₁ and R₂ as selected and shown in step 7, provided that the ratio is correct. This allows selection of larger values of R₁ and R₂ to minimize divider current.
9. A filter capacitor can be used across R_f to limit bandwidth and minimize noise (f_c = 50 kHz in this example).
   ${\mathrm{C}}_{\mathrm{f}}=\frac{1}{2\mathrm{\pi }{\mathrm{R}}_{\mathrm{f}}{\mathrm{f}}_{\mathrm{c}}}=\frac{1}{2\mathrm{\pi }\left(100\mathrm{k}\mathrm{\Omega }\right)\left(50\mathrm{k}\mathrm{H}\mathrm{z}\right)}=31.8\mathrm{p}\mathrm{F}\mathrm{ }\left(33\mathrm{p}\mathrm{F}\mathrm{ }\mathrm{s}\mathrm{t}\mathrm{a}\mathrm{n}\mathrm{d}\mathrm{a}\mathrm{r}\mathrm{d}\mathrm{ }\mathrm{v}\mathrm{a}\mathrm{l}\mathrm{u}\mathrm{e}\right)$

DC Transfer Characteristics

The following images show the DC Transfer function for the standard and buffered version of the circuit. Note that the buffered version is more accurate. Also note that the values selected in the buffered version, use the same ratios, but the magnitudes are adjusted. The buffered version decreased the feedback network impedance for better noise, and increased the divider network for better power dissipation. Note that the inaccuracy in the transfer function can be accounted for with a simple calibration (see the Calibration video).

Figure 1-1 DC Transfer Characteristics for Unbuffered Circuit

Figure 1-2 DC Transfer Characteristics for Buffered Circuit

AC Transfer Characteristics

The capacitor C_f sets the cutoff frequency to 100 kHz. This causes the gain of the amplifier to roll-off until gain is 1 V/V or 0 dB. At higher frequency the bandwidth limitations of the amplifier causes gain to roll-off again. The expected bandwidth of 50 kHz compares well to the simulated 48.5 kHz. Additional detail on bandwidth limitations are given in the Bandwidth video series.

Figure 1-3 AC Transfer Characteristics for Level Translator

Noise Simulation

Total noise is approximately 32.9 µV_RMS. Peak-to-peak is approximately 6 × RMS = 197 µVpp. For more information on noise analysis and optimization see the Noise video series. Note that the noise of the buffered version is lower because the voltage divider uses lower resistor values which minimizes total noise.

Figure 1-4 Total RMS Noise for Level Translator

Stability

This circuit is stable for capacitive loads from 0 pF to 120 pF. The analysis below shows 48.2°C of phase margin for a 120-pF load (45°C and better is considered stable). For more information on stability see the Stability video series.

Figure 1-5 Stability of Level Translator Circuit

Design Featured Devices and Alternative Parts

This design works with most amplifiers that accept high-voltage ±15-V supplies. Depending on the application the key parameters can be different. The following table shows three different options representing different categories of devices. Package-trimmed devices have good offset and offset drift by adjusting internal device resistors, zero-drift devices use an internal calibration to reduce offset and drift, and general-purpose are optimized for best cost. When using a zero-drift option, a best practice is to keep the total feedback impedance less than 10 kΩ (R_f || (R_g + R₁ || R₂) < 10 kΩ). This is recommended to avoid translating bias current into offset voltage. Click on the other possible devices link for a list of other options in the same category.

Design References

1. See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.
2. See circuit TINA SPICE simulation file sbomcf8.
3. See circuit PSPICE simulation file sbomcf7.
4. For more information on many op-amp topics including common-mode range, output swing, bandwidth, and how to drive an ADC please visit TI Precision Labs.
5. See the OPAx206 Input-Overvoltage-Protected, 4-μV, 0.08-μV/°C, Low-Power Super Beta, e-trim™ Op Amps data sheet for layout guidelines.