During power on of the ADS833x, the digital interface supply voltage (VBD) should not exceed the analog supply voltage (VA). This condition is specified in the Power-Supply Requirements section of the Electrical Characteristics tables. If the analog and digital interface supplies for the converter are not generated by a single voltage source, TI recommends to power on the analog supply and wait for it to reach its final value before the digital interface supply is activated. Furthermore, the voltages applied to the analog input pins (IN_X, ADCIN) and digital input pins (RESET, FS/CS, SCLK, SDI, and CONVST) should not exceed the voltages on VA and VBD, respectively, during the power-on sequence. This requirement prevents these input pins from powering the ADS833x through the ESD protection diodes and circuitry, and causing an increase in current consumption, until both supplies are fully powered (see the Electrical Characteristics and Figure 34 for further details).

Communication with the ADS833x, such as initiating a conversion with CONVST or writing to the Configuration register, should not occur for a minimum of 2 μs after the analog and digital interface supplies have finished the power-on sequence and reached the respective final values in the system. This time is required for the internal POR to activate and place the digital core of the device into the default mode of operation. This minimum delay time must also be adhered to whenever a reset condition occurs (see the section for additional information).