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SBAS439C August 2008 – July 2015 DAC8311 , DAC8411

PRODUCTION DATA.

8 Detailed Description

8.1 Overview

The DAC8x11 family of devices are low-power, single-channel, voltage output DACs. These devices are monotonic by design, provide excellent linearity, and minimize undesired code-to-code transient voltages while offering an easy upgrade path within a pin-compatible family. All devices use a versatile, 3-wire serial interface that operates at clock rates of up to 50 MHz and is compatible with standard SPI, QSPI, Microwire, and digital signal processor (DSP) interfaces.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 DAC Section

The DAC8311 and DAC8411 are fabricated using Texas Instruments' proprietary HPA07 process technology. The architecture consists of a string DAC followed by an output buffer amplifier. Because there is no reference input pin, the power supply (AV_DD) acts as the reference. Figure 74 shows a block diagram of the DAC architecture.

Figure 74. DAC8x11 Architecture

The input coding to the DAC8311 and DAC8411 is straight binary, so the ideal output voltage is given by:

where

n = resolution in bits; either 14 (DAC8311) or 16 (DAC8411).
D = decimal equivalent of the binary code that is loaded to the DAC register; it ranges from 0 to 16,383 for the 14-bit DAC8311, or 0 to 65,535 for the 16-bit DAC8411.

8.3.2 Resistor String

The resistor string section is shown in Figure 75. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. The resistor string architecture is inherently monotonic.

DAC8311 DAC8411 ai_res_string_bas439.gif

Figure 75. Resistor String

8.3.3 Output Amplifier

The output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range of 0V to AV_DD. The output amplifier is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the Typical Characteristics section for each device. The slew rate is 0.7 V/μs with a half-scale settling time of typically 6 μs with the output unloaded.

8.3.4 Power-On Reset to Zero-Scale

The DAC8x11 contains a power-on reset circuit that controls the output voltage during power up. On power up, the DAC register is filled with zeros and the output voltage is 0 V. The DAC register remains that way until a valid write sequence is made to the DAC. This design is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up.

The occurring power-on glitch impulse is only a few mV (typically, 17 mV; see Figure 31, Figure 72, or Figure 31).

8.4 Device Functional Modes

8.4.1 Power-Down Modes

The DAC8x11 contains four separate modes of operation. These modes are programmable by setting two bits (PD1 and PD0) in the control register. Table 3 shows how the state of the bits corresponds to the mode of operation of the device.

Table 3. Modes of Operation for the DAC8x11

PD1	PD0	OPERATING MODE
NORMAL MODE
0	0	Normal Operation
POWER-DOWN MODES
0	1	Output 1 kΩ to GND
1	0	Output 100 kΩ to GND
1	1	High-Z

When both bits are set to 0, the device works normally with a standard power consumption of typically 80 μA at 2 V. However, for the three power-down modes, the typical supply current falls to 0.5 μA at 5 V, 0.4 μA at 3 V, and 0.1 μA at 2.0 V. Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. The advantage of this architecture is that the output impedance of the part is known while the part is in power-down mode. There are three different options. The output is connected internally to GND either through a 1-kΩ resistor or a 100-kΩ resistor, or is left open-circuited (High-Z). See Figure 76 for the output stage.

Figure 76. Output Stage During Power-Down

All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 50 μs for AV_DD = 5 V and AV_DD = 3 V. See the Typical Characteristics: AVDD = 5 V for each device for more information.

8.5 Programming

8.5.1 DAC8311 Serial Interface

The DAC8311 has a 3-wire serial interface (SYNC, SCLK, and DIN) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See Figure 1 for an example of a typical write sequence.

8.5.1.1 DAC8311 Input Shift Register

The input shift register is 16 bits wide, as shown in Figure 77. The first two bits (PD0 and PD1) are reserved control bits that set the desired mode of operation (normal mode or any one of three power-down modes) as indicated in Table 3.

The write sequence begins by bringing the SYNC line low. Data from the DIN line are clocked into the 16-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the DAC8311 compatible with high-speed DSPs. On the 16th falling edge of the serial clock, the last data bit is clocked in and the programmed function is executed.

At this point, the SYNC line may be kept low or brought high. In either case, it must be brought high for a minimum of 20 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence.

8.5.1.2 DAC8311 SYNC Interrupt

In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th falling edge. However, bringing SYNC high before the 16th falling edge acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents or a change in the operating mode occurs, as shown in Figure 78.

Figure 77. DAC8311 Data Input Register

DB15

DB14

DB0

PD1

PD0

D13

D12

D11

D10

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

DAC8311 DAC8411 ai_sync_int_14bit_bas439.gif

Figure 78. DAC8311 SYNC Interrupt Facility

8.5.2 DAC8411 Serial Interface

The DAC8411 has a 3-wire serial interface (SYNC, SCLK, and DIN) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See the Figure 1 for an example of a typical write sequence.

8.5.2.1 DAC8411 Input Shift Register

The input shift register is 24 bits wide, as shown in Figure 79. The first two bits are reserved control bits (PD0 and PD1) that set the desired mode of operation (normal mode or any one of three power-down modes) as indicated in Table 3. The last six bits are don't care.

The write sequence begins by bringing the SYNC line low. Data from the DIN line are clocked into the 24-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the DAC8411 compatible with high-speed DSPs. On the 18th falling edge of the serial clock, the last data bit is clocked in and the programmed function is executed. The last six bits are don't care.

The SYNC line may be brought high after the 18th bit is clocked in because the last six bits are don't care.

8.5.2.2 DAC8411 SYNC Interrupt

In a normal write sequence, the SYNC line is kept low for 24 falling edges of SCLK and the DAC is updated on the 18th falling edge, ignoring the last six don't care bits. However, bringing SYNC high before the 18th falling edge acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents or a change in the operating mode occurs, as shown in Figure 80.

Figure 79. DAC8411 Data Input Register

DB23
PD1	PD0	D15	D14	D13	D12	D11	D10


D9	D8	D7	D6	D5	D4	D3	D2

DB7	DB6	DB5
D1	D0	X	X	X	X	X	X

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

DAC8311 DAC8411 ai_sync_int_16bit_bas439.gif

Figure 80. DAC8411 SYNC Interrupt Facility