米6体育平台手机版

SBAS654G June 2014 – January 2020

PRODUCTION DATA.

over operating free-air temperature range (unless otherwise noted)

PARAMETER		MIN	TYP	MAX	UNIT
t_CLK	CLKIN, CLKIN_N clock period	49.75	50	200	ns
t_HIGH	CLKIN, CLKIN_N clock high time	19.9	25	120	ns
t_LOW	CLKIN, CLKIN_N clock low time	19.9	25	120	ns
t_D	Falling edge of CLKIN, CLKIN_N to DOUT, DOUT_N valid delay, C_LOAD = 5 pF	0		15	ns
t_ISTART	Interface startup time (DVDD at 3.0 V min to DOUT, DOUT_N valid with AVDD ≥ 4.5 V)	32		32	CLKIN cycles
t_ASTART	Analog startup time (AVDD step up to 4.5 V with DVDD ≥ 3.0 V)		1		ms

Figure 1. Digital Interface Timing

Figure 2. Digital Interface Startup Timing