SBAU260 April 2016
The register map settings file is provided for use when developing your own code. The file can be included in your project to use the settings from the evaluation software.
The first section contains #defines that provide constants for:
The second section contains a struct definition and an array of the structs that contain the register address and value for each of the writeable registers:
/* ADS131A0x Register Settings Export */
/******************************************************************************/
/* This file contains the register map settings stub */
// General defines
#define ADS131A0x_REGISTER_COUNT 17
/* Register #define values (register address and value) */
/******************************************************************************/
/* This section contains the defines for register address and register settings */
/* Register address defines - All registers */
#define ID_MSB_ADDRESS 0x00
#define ID_LSB_ADDRESS 0x01
#define STAT_1_ADDRESS 0x02
#define STAT_P_ADDRESS 0x03
#define STAT_N_ADDRESS 0x04
#define STAT_S_ADDRESS 0x05
#define ERROR_CNT_ADDRESS 0x06
#define STAT_M2_ADDRESS 0x07
#define A_SYS_CFG_ADDRESS 0x0B
#define D_SYS_CFG_ADDRESS 0x0C
#define CLK1_ADDRESS 0x0D
#define CLK2_ADDRESS 0x0E
#define ADC_ENA_ADDRESS 0x0F
#define ADC1_ADDRESS 0x11
#define ADC2_ADDRESS 0x12
#define ADC3_ADDRESS 0x13
#define ADC4_ADDRESS 0x14
/* Register value defines - Only writeable registers*/
#define A_SYS_CFG_VALUE 0x60
#define D_SYS_CFG_VALUE 0x3C
#define CLK1_VALUE 0x08
#define CLK2_VALUE 0x86
#define ADC_ENA_VALUE 0x00
#define ADC1_VALUE 0x00
#define ADC2_VALUE 0x00
#define ADC3_VALUE 0x00
#define ADC4_VALUE 0x00
/* Register array constant and structure */
/******************************************************************************/
/* This section contains the structure definition and array of structures containing writable register settings*/
struct registerData
{
int address,
int value
}
const registerData ADS131A0x_Registers[] =
{
{ 0x000B, 0x0060 }, // A_SYS_CFG
{ 0x000C, 0x003C }, // D_SYS_CFG
{ 0x000D, 0x0008 }, // CLK1
{ 0x000E, 0x0086 }, // CLK2
{ 0x000F, 0x0000 }, // ADC_ENA
{ 0x0011, 0x0000 }, // ADC1
{ 0x0012, 0x0000 }, // ADC2
{ 0x0013, 0x0000 }, // ADC3
{ 0x0014, 0x0000 }, // ADC4
};