3.1 SPI Communication

The ADS131B04-Q1EVM supports limited interface modes as detailed in the ADS131B04-Q1 data sheet. The ADS131B04-Q1 uses an SPI-compatible interface to configure the device and retrieve conversion data. SPI communication on the ADS131B04-Q1 is performed in frames. Each SPI communication frame consists of several words. The word size is configurable as either 16 bits, 24 bits (default), or 32 bits by programming the WLENGTH[1:0] bits in the MODE register.

Additionally, the DRDY pin indicates when conversion data are available to be read by the master. The DRDY_SEL[1:0] bits, DRDY_HIZ bit, and the DRDY_FMT bit in the MODE register control the behavior of the DRDY pin.

For this EVM not all modes and functions for this SPI communication are supported. Functions not supported are disabled in the EVM GUI software. For more information about the SPI communication, see the ADS131B04-Q1 data sheet.