Although the EVM GUI does not allow direct access to the levels and timing configuration of the ADC digital interface, the EVM GUI does give users high-level control over many other functions of the ADS131A04 including: internal clock dividers, oversampling ratio (OSR), and number of samples to be captured. Figure 7-1 identifies the input parameters of the GUI (as well as their default values) through which the various functions of the ADS131A04 can be exercised.

Figure 7-1 EVM GUI Global Input Parameters

There are four pages available in the ADS131A04EVM GUI. The information area displays the results of each of the pages. Each of these pages display a different control or measurement of the device. The Register Map Config page is used to read and write to the registers of the device. The Time Domain Display page is used to collect a set of data from the device and display the result. The Spectral Analysis page can compute the FFT of the collected data, and the Histogram Analysis page shows a histogram of the collected data and displays basic statistics of the result.

The Single Commands section allows for direct control of the device for three basic functions. First the Reset button sends a signal to the RESET pin to reset the device. The Standby button puts the device into a low-power state in which all channels are disabled, and the reference and other non-essential circuitry are powered down. The Wakeup button exits the standby mode.

The interface section also sets the data rate by setting the internal clock dividers and OSR in the ADC. Finally, this section may used to set the power modes in the registers. The ADS131A04 has two power modes (Low-Power and High-Resolution), which is configured in the A_SYS_CFG register (bit 6). This is used in conjunction with the jumper settings of JP4 for the CLKIN pin, as outlined in Table 3-2. This information is also discussed in Section 3.2.

The Clock and Sampling Rate section allows the user to specify a target SCLK frequency (in Hz) and the GUI tries to match this frequency as closely as possible by changing the PHI PLL settings, but the achievable frequency may differ from the target value entered. This section also displays the sampling rate of the ADC as controlled by the internal clock dividers and the OSR.

The GUI is switched between hardware mode and simulation mode by checking and unchecking the Connected to Hardware box in the top right area of the screen at any time.